本文深入探讨了NOC（Network-on-Chip）架构的内在机制，包括其在深亚微米设计中遇到的布线定时问题、更适合GAL范式的应用、仲裁延迟与实例特定仲裁器的使用、总线带宽共享、分布式路由决策和可重新配置的开关等关键特性。同时，文章还指出了NOC架构的优缺点，如硅成本较低但面积成本较高、简单的总线-IP内核接口与复杂的网络-IP内核接口、已知的设计指导原则以及新兴的设计范式。
Noc(Network onchip )
-Each integrated IP core adds bus load capacitance
+Only point-to-point one-way links are used
-Bus timing problems in deep sub-micron designs
+Better suited for GALS paradigm
-Arbiter delay grows with no of masters. Instance-specific arbiter
+Distributed routing decisions. Reinstantiable switches
-Bus bandwidth is shared among all masters
+Bus bandwidth scales with network dimension
+After bus is granted, bus access latency is null
-Unpredictable latency due to network congestion problems
+Very low silicon cost
-High area cost
+Simple bus-IP core interface
-Network-IP core interface can be very complex (e.g. packetization,..)
+Design guidelines are well known
-New design paradigm
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