[NVME] CMBLOC-Controller Memory Buffer Location

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已于 2025-01-23 11:29:25 修改

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于 2025-01-22 22:15:35 首次发布

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This optional register defines the location of the Controller Memory Buffer (refer to section 4.7).

If the controller does not support the Controller Memory Buffer (CAP.CMBS), this register is reserved.

If the controller supports the Controller Memory Buffer and CMBMSC.CRE is cleared to ‘0’, this register shall be cleared to 0h

Bits	Type	Reset	Description
31:12	RO	Impl Spec	Offset (OFST) Indicates the offset of the Controller Memory Buffer in multiples of the Size Unit specified in CMBSZ (如果 CMBSZ 中指定的大小单元是 4 字节，而这个参数的值是 3，那么控制器内存缓冲区的偏移量就是 12 字节)
11:09	RO	000b	Reserved
08	RO	Impl Spec	CMB Queue Dword Alignment (CQDA) 1:CDW11.PC is set to ‘1’; and the address poin