Jinlong_Xu的博客

MSHR(Miss Status and Handling Register)    On a cache hit, a request will be served by sending data to the register file immediately. On a cache miss, the miss handling logic will first check the mi

Verilog用于模块的测试Verilog可以用来描述变化的测试信号，描述测试信号的变化和测试过程的模块也称为testbench。在这里，我写一个示例，大家能明白该怎么写了。首先要写功能模块——二选一多路选择器。代码如下：`timescale 1ns / 1ps////////////////////////////////////////////////////////////