romInit.s(平台S3C2410,Vxworks5.5)
主要完成了硬件初始化,例如设置UART0可以接收数据,禁用所有中断,初始化DRAM,设置MMU单元,设置时钟频率FCLK和PCLK、HCLK等
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "regs.h"
#include "config.h"
#include "arch/arm/mmuArmLib.h"
/* add by lyx for 2410 in 0609*/
#include "option.a"
#include "2410addr.s"
.data
.globl VAR(copyright_wind_river) @全局符号
.long VAR(copyright_wind_river) @定义变量为long整型copyright_wind_river由symTbl.c导入IMPORT int copyright_wind_river;
/* internals */
.globl FUNC(romInit) /* start of system code */
.globl VAR(sdata) /* start of data */
.globl _sdata
/* externals */
.extern FUNC(romStart) /* system initialization routine */@在bootInit.c中定义
_sdata:
VAR_LABEL(sdata)
.asciz "start of data"
.balign 4
/* variables */
.data
.text@代码段
.balign 4@4字节对齐
/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
* (
* int startType /@ only used by 2nd entry point @/
* )
* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/
_ARM_FUNCTION(romInit)
_romInit: /*ARM跳转表*/
B cold /*reset*/
B _romUndef/*未定义指令*/
B _romSwi/*软中断*/
B _romPrefetch/*预取指令异常*/
B _romDataAbort/*数据异常*/
B cold/*保留*/
B _romIRQ/*IRQ*/
B _romIRQ/*快速中断*/
/*
=====sysLib.h中定义=============
/* system restart types */
#define BOOT_NORMAL 0x00 /* normal reboot with countdown */
#define BOOT_NO_AUTOBOOT 0x01 /* no autoboot if set */
#define BOOT_CLEAR 0x02 /* clear memory if set */
#define BOOT_QUICK_AUTOBOOT 0x04 /* fast autoboot if set */
/* for backward compatibility */
#define BOOT_WARM_AUTOBOOT BOOT_NORMAL
#define BOOT_WARM_NO_AUTOBOOT BOOT_NO_AUTOBOOT
#define BOOT_WARM_QUICK_AUTOBOOT BOOT_QUICK_AUTOBOOT
#define BOOT_COLD BOOT_CLEAR
*/
cold:
MOV r0, #BOOT_COLD /* fall through to warm boot entry *//*将BOOT_COLD值写入r0寄存器,BOOT_COLD在sysLib.h中定义*/
warm:@热启动部分
B start
/* copyright notice appears at beginning of ROM (in TEXT segment) */
.ascii "Copyright 1999-2001 ARM Limited"
.ascii "\nCopyright 1999-2001 Wind River Systems, Inc."
.balign 4
start:
/*
* There have been reports of problems with certain boards and
* certain power supplies not coming up after a power-on reset,
* and adding a delay at the start of romInit appears to help
* with this.
*/
MOV R14,R0 @保存返回地址到r14
/*
* CPU INTERRUPTS DISABLED
*
* disable individual interrupts in the interrupt controller
*/
@设置GPH1为nRTS0
ldr r1,=0x56000070 //PCONH
ldr r0,[r1]
bic r0,r0,#0x00000008
orr r0,r0,#0X00000004
str r0,[r1]
@GPH1DATA = 0,nRTS=0,请求发送数据,TXD0,RXD0
ldr r1,=0x56000074 //PDATH
ldr r0,[r1]
bic r0,r0,#0x0002 //PH1=0
str r0,[r1]
ldr r0,=WTCON @ watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0xffffffff @ all interrupt disable
str r1,[r0]
ldr r0,=INTSUBMSK
ldr r1,=0x7ff @ all sub interrupt disable
str r1,[r0]
ldr r0,=SRCPND
ldr r1,=0xffffffff @ clear all interrupt source
str r1,[r0]
ldr r0,=INTPND
ldr r1,=0xffffffff @ clear all interrupt pend
str r1,[r0]
ldr r0,=CLKDIVN
ldr r1,=0x03 @ HCLK=FLCK/2 PCLK=FCLK/4 busfrq=50Mhz
str r1,[r0]
ldr r0,=CLKCON
ldr r1,=0x7fff0 @ all clk enable
str r1,[r0]
ldr r0,=UPLLCON
ldr r1,=((40<<12)+(2<<4)+1) @ Fin=8MHz,Fout=FCLK in option.a,configure the Upll to 48MHZ=(40+8)*8M/((2+2)*2)
str r1,[r0]
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) @ Fin=8MHz,Fout=FCLK in option.a
str r1,[r0]
/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^文件option.a^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.EQU FCLK, 200000000 @must modify in 2410addr.h too for 8M fin,定义FCLK=200MHZ
.EQU FIN, 8000000
.IF (FIN == 8000000)
@.EQU FCLK, 200000000
.EQU HCLK, (FCLK/2)
.EQU PCLK, (FCLK/4)
.EQU UCLK, PCLK
.IF (FCLK == 100000000)
.EQU M_MDIV, 0x43 @FIN=8.0MHz Fout=100.0MHz
.EQU M_PDIV, 0x1
.EQU M_SDIV, 0x1
.ENDIF
.IF (FCLK == 150000000)
.EQU M_MDIV, 0x8E @FIN=8.0MHz Fout=150.0MHz
.EQU M_PDIV, 0x2
.EQU M_SDIV, 0x1
.ENDIF
.IF (FCLK == 200000000)@在这里定义MDIV,M_PDIV,M_SDIV的值
.EQU M_MDIV, 0xC0 @FIN=8.0MHz Fout=200.0MHz
.EQU M_PDIV, 0x2
.EQU M_SDIV, 0x1
.ENDIF*/
@@设置内存
/*Special Registers*/
ldr r0,L$_SMRDATA @must convert here
ldmia r0,{r1-r13}@[R0]=>{R1->R13}
ldr r0,=BWSCON @BWSCON Address
stmia r0,{r1-r13}@{r1-r13}=>{r0}
/* Setup MMU Control Register */
MOV r1, #MMU_INIT_VALUE /* Defined in mmuArmLib.h */
ORR r1, r1, #0xc0000000 /* 2410特有的控制位,设置cpu工作在异步时钟*/
#if defined(INTEGRATOR_EARLY_I_CACHE_ENABLE)
ORR r1, r1, #MMUCR_I_ENABLE /* no define zj ##conditionally enable Icache*/ @@这个一般是在config.h中定义,但是ARM920T默认情况下不开
#endif
MCR CP_MMU, 0, r1, c1, c0, 0 /* Write to MMU CR */
/*
* If MMU was on before this, then we'd better hope it was set
* up for flat translation or there will be problems. The next
* 2/3 instructions will be fetched "translated" (number depends
* on CPU).
*
* We would like to discard the contents of the Write-Buffer
* altogether, but there is no facility to do this. Failing that,
* we do not want any pending writes to happen at a later stage,
* so drain the Write-Buffer, i.e. force any pending writes to
* happen now.
*/
MOV r1, #0 /* data SBZ */
MCR CP_MMU, 0, r1, c7, c10, 4 /* drain write-buffer 排空写缓冲区*/
/* Flush (invalidate) both I and D caches */
MCR CP_MMU, 0, r1, c7, c7, 0 /* R1 = 0 from above, data SBZ*/
/*
* Set Process ID Register to zero, this effectively disables
* the process ID remapping feature.
*/
MOV r1, #0
MCR CP_MMU, 0, r1, c13, c0, 0
/* disable interrupts in CPU and switch to SVC32 mode */
MRS r1, cpsr
BIC r1, r1, #MASK_MODE
ORR r1, r1, #MODE_SVC32 | I_BIT | F_BIT
MSR cpsr, r1
/* 因为看门狗芯片精度的问题,有可能在系统起来之前就复位,因此先喂狗,使用定时器3喂狗,added by xp 2012-6-14*/
ldr r0,=0x51000004 /*配置TCFG1*/
ldr r1,[r0]
and r1,r1,#0xffff0fff@选择1/2MUX作为PWM TIMER3的输入
str r1,[r0]
ldr r0,=0x51000004
ldr r1,[r0]
orr r1,r1,#0x3000@选择1/16MUX作为PWM TIMER3的输入
str r1,[r0]
ldr r0,=0x51000030
ldr r1,=1000@Timer 3 count buffer register设置timer3计数器值为1000
str r1,[r0]
ldr r0,=0x51000034
ldr r1,=500@设置timer3比较值为500 Timer 3 compare buffer register
str r1,[r0]
ldr r0,=0x51000008 @TCON
ldr r1,[r0]
and r1,r1,#0xfff0ffff@清除有关timer3的配置
str r1,[r0]
ldr r0,=0x51000008
ldr r1,[r0]
orr r1,r1,#0x20000@Update TCNTB3 & TCMPB3
str r1,[r0]
ldr r0,=0x51000008
ldr r1,[r0]
and r1,r1,#0xfff0ffff@清除有关timer3的配置
str r1,[r0]
ldr r0,=0x51000008
ldr r1,[r0]
orr r1,r1,#0x90000@Interval mode (auto reload);Start for Timer 3;启动定时器3
str r1,[r0]
ldr r0,=0x56000010
ldr r1,[r0]
and r1,r1,#0xffffff3f@清除GPB3
str r1,[r0]
ldr r0,=0x56000010
ldr r1,[r0]
orr r1,r1,#0x80 @设置GPB3为TOUT3
str r1,[r0]
MOV r0, r14 /* restore starttype to r0 from r14 */
/* jump to C entry point in ROM: routine - entry point + ROM base */
LDR sp, L$_STACK_ADDR
@这里设置SP的原因参考下图
MOV fp, #0 /* zero frame pointer */
LDR pc, L$_rStrtInRom @go to romStart function
@@@@@@@@@@@@@异常处理
_ARM_FUNCTION(romUndef)
_romUndef:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promUndef
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romSwi)
_romSwi:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promSwi
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romPrefetch)
_romPrefetch:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promFth
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romDataAbort)
_romDataAbort:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promAbo
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romIRQ)
_romIRQ:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promIRQ
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
/******************************************************************************/
/*
* PC-relative-addressable pointers - LDR Rn,=sym is broken
* note "_" after "$" to stop preprocessor performing substitution
*/
.balign 4
L$_rStrtInRom:
.long ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)@ROM_TEXT_ADRS在Makefile中指定
L$_STACK_ADDR:
.long STACK_ADRS@_romInit
L$_promUndef:
.long S3C_EXC_BASE + 0@在2410addr.S中定义
L$_promSwi:
.long S3C_EXC_BASE + 4
L$_promFth:
.long S3C_EXC_BASE + 8
L$_promAbo:
.long S3C_EXC_BASE + 12
L$_promIRQ:
.long S3C_EXC_BASE + 20
L$_SMRDATA:
.long ROM_TEXT_ADRS + SMRDATA - FUNC(romInit)
/*;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized. *
;*****************************************************************
;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 64Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz.
;**********MEMORY CONTROL PARAMETERS*******************************/
.GLOBAL BUSWIDTH @max. bus width for the GPIO configuration
@ BUSWIDTH : 16,32
.EQU BUSWIDTH, 32
@ BWSCON
.EQU DW8 , (0x0)
.EQU DW16 , (0x1)
.EQU DW32 , (0x2)
.EQU WAIT , (0x1<<2)
.EQU UBLB , (0x1<<3)
.ifeq BUSWIDTH-16
.EQU B1_BWSCON, (DW16)
.EQU B2_BWSCON, (DW16)
.EQU B3_BWSCON, (DW16)
.EQU B4_BWSCON, (DW16)
.EQU B5_BWSCON, (DW16)
.EQU B6_BWSCON, (DW16)
.EQU B7_BWSCON, (DW16)
.endif
.ifeq BUSWIDTH-32
.EQU B1_BWSCON, (DW16)
.EQU B2_BWSCON, (DW16)
.EQU B3_BWSCON, (DW16)
.EQU B4_BWSCON, (DW16)
.EQU B5_BWSCON, (DW16)
.EQU B6_BWSCON, (DW16)
.EQU B7_BWSCON, (DW16)
.endif
@ BANK0CON
.EQU B0_Tacs , 0x0 @ 0clk
.EQU B0_Tcos , 0x0 @ 0clk
.EQU B0_Tacc , 0x7 @ 14clk
.EQU B0_Tcoh , 0x0 @ 0clk
.EQU B0_Tah , 0x0 @ 0clk
.EQU B0_Tacp , 0x0
.EQU B0_PMC , 0x0 @ normal
@ BANK1CON
.EQU B1_Tacs , 0x0 @ 0clk
.EQU B1_Tcos , 0x0 @ 0clk
.EQU B1_Tacc , 0x7 @ 14clk
.EQU B1_Tcoh , 0x0 @ 0clk
.EQU B1_Tah , 0x0 @ 0clk
.EQU B1_Tacp , 0x0
.EQU B1_PMC , 0x0 @ normal
@ Bank 2 parameter
.EQU B2_Tacs , 0x0 @ 0clk
.EQU B2_Tcos , 0x0 @ 0clk
.EQU B2_Tacc , 0x7 @ 14clk
.EQU B2_Tcoh , 0x0 @ 0clk
.EQU B2_Tah , 0x0 @ 0clk
.EQU B2_Tacp , 0x0
.EQU B2_PMC , 0x0 @ normal
@ Bank 3 parameter
.EQU B3_Tacs , 0x0 @ 0clk
.EQU B3_Tcos , 0x0 @ 0clk
.EQU B3_Tacc , 0x7 @ 14clk
.EQU B3_Tcoh , 0x0 @ 0clk
.EQU B3_Tah , 0x0 @ 0clk
.EQU B3_Tacp , 0x0
.EQU B3_PMC , 0x0 @ normal
@ Bank 4 parameter
.EQU B4_Tacs , 0x0 @ 0clk
.EQU B4_Tcos , 0x0 @ 0clk
.EQU B4_Tacc , 0x7 @ 14clk
.EQU B4_Tcoh , 0x0 @ 0clk
.EQU B4_Tah , 0x0 @ 0clk
.EQU B4_Tacp , 0x0
.EQU B4_PMC , 0x0 @ normal
@ Bank 5 parameter
.EQU B5_Tacs , 0x0 @ 0clk
.EQU B5_Tcos , 0x0 @ 0clk
.EQU B5_Tacc , 0x7 @ 14clk
.EQU B5_Tcoh , 0x0 @ 0clk
.EQU B5_Tah , 0x0 @ 0clk
.EQU B5_Tacp , 0x0
.EQU B5_PMC , 0x0 @ normal
@ Bank 6 parameter
.EQU B6_MT , 0x3 @ SDRAM
@ B6_Trcd , 0x0 @ 2clk
.EQU B6_Trcd , 0x1 @ 3clk
.EQU B6_SCAN , 0x1 @ 9bit
@ Bank 7 parameter
.EQU B7_MT , 0x0 @ SRAM
@ B7_Trcd , 0x0 @ 2clk
.EQU B7_Trcd , 0x0 @ 3clk
.EQU B7_SCAN , 0x0 @ 9bit
@ REFRESH parameter
.EQU REFEN , 0x1 @ Refresh enable
.EQU TREFMD , 0x0 @ CBR(CAS before RAS)/Auto refresh
.EQU Trp , 0x0 @ 2clk
.EQU Trc , 0x3 @ 7clk
.EQU Tchr , 0x2 @ 3clk
.EQU REFCNT , 1269 @489 period=15.6us, HCLK=100Mhz, (2048+1-15.6*100)
@1269 period=15.6us, HCLK=50Mhz, (2048+1-15.6*50)
/*;************************************************
;bank0 16bit BOOT ROM
;bank1 8bit NandFlash
;bank2 16bit IDE
;bank3 8bit UDB
;bank4 rtl8019
;bank5 ext
;bank6 16bit SDRAM
;bank7 16bit SDRAM*/
.balign 4
SMRDATA:
# Memory configuration should be optimized for best performance
# The following parameter is not optimized.
# Memory access cycle parameter strategy
# 1) The memory settings is safe parameters even at HCLK=75Mhz.
# 2) SDRAM refresh period is for HCLK=75Mhz.
.long ((B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) @ GCS0
.long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) @ GCS1
.long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) @ GCS2
.long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) @ GCS3
.long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) @ GCS4
.long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) @ GCS5
.long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) @ GCS6
.long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) @ GCS7
.long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.long 0x10 //SCLK power down mode, BANKSIZE 32M/32M 16-8M 17-16M
.long 0x20 //MRSR6 CL=2clk
.long 0x20 //MRSR7