- Interrupts
- Maskable interrupts, which are signalled via the INTR pin.
- Nonmaskable interrupts, which are signalled via the NMI (Non-Maskable Interrupt) pin.
- Exceptions
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Faults
- Faults are exceptions that are reported "before" theinstruction causingthe exception. Faults are either detected beforethe instruction begins to execute, or during execution of theinstruction. If detected during the instruction, the fault isreported with the machine restored to a state that permits theinstruction to be restarted. Traps
- A trap is an exception that is reported at the instruction boundary immediately after the instruction in which the exception was detected. Aborts
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An abort is an exception that permits neither precise location of the instruction causing the exception nor restart of the program that caused the exception. Aborts are used to report severe errors,such as hardware errors and inconsistent or illegal values in system tables.
Table 1. Interrupt and Exception ID Assignments Identifier Description 0 Divide error 1 Debug exceptions 2 Nonmaskable interrupt 3 Breakpoint (one-byte INT 3 instruction) 4 Overflow (INTO instruction) 5 Bounds check (BOUND instruction) 6 Invalid opcode 7 Coprocessor not available 8 Double fault 9 (reserved) 10 Invalid TSS 11 Segment not present 12 Stack exception 13 General protection 14 Page fault 15 (reserved) 16 Coprecessor error 17-31 (reserved) 32-255 Available for external interrupts via INTR pin


Basics of Protected Control Transfer
Exceptions and interrupts are both" protected control transfers,"which cause the processor to switch from user to kernel mode(CPL=0) without giving the user-mode code any opportunity to interfere with the functioning of the kernel or other environments.Interrupt is asynchronous, exception is synchronous. X86 use IDT(Interrupt Descriptor Table, a mini GDT for interrupt) and TSS(Task State Segment, to save the context of current task).
Example
Let's say the processor is executing code in a user environment and encounters a divide instruction that attempts to divide by zero.
- The processor switches to the stack defined by theSS0 and ESP0 fields of the TSS,which in JOS will hold the values
GD_KDandKSTACKTOP, respectively. - The processor pushes the exception parameters on the kernel stack, starting at address
KSTACKTOP:+--------------------+ KSTACKTOP | 0x00000 | old SS | " - 4 | old ESP | " - 8 | old EFLAGS | " - 12 | 0x00000 | old CS | " - 16 | old EIP | " - 20 <---- ESP +--------------------+ - Because we're handling a divide error,which is interrupt vector 0 on the x86,the processor reads IDT entry 0 and setsCS:EIP to point to the handler function described by the entry.
- The handler function takes control and handles the exception,for example by terminating the user environment.
For certain types of x86 exceptions,in addition to the "standard" five words above,the processor pushes onto the stack another word containing an error code.The page fault exception, number 14,is an important example.See the 80386 manual to determine for which exception numbers the processor pushes an error code,and what the error code means in that case.When the processor pushes an error code,the stack would look as follows at the beginning of the exception handler when coming in from user mode:
+--------------------+ KSTACKTOP
| 0x00000 | old SS | " - 4
| old ESP | " - 8
| old EFLAGS | " - 12
| 0x00000 | old CS | " - 16
| old EIP | " - 20
| error code | " - 24 <---- ESP
本文介绍了x86架构下的中断和异常处理机制,包括可屏蔽中断、不可屏蔽中断、故障、陷阱及中止等类型,并详细解释了它们的区别及处理器如何进行处理。此外,还讨论了保护模式下控制转移的基本原理。
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