“春节快乐”Verilog代码

原文参考链接：https://blog.youkuaiyun.com/weixin_44884357/article/details/104688665

用Verilog显示中文字符的例子

`timescale 1ns / 1ps

module gen_line
#(
parameter COL_CNT = 16'd80,
parameter TURN = 1'b1
)
(
input [127:0]row_data,
output odata,

input bit_clk,       //100ns
input bit1_roll_clk, //2ns
input reset_p
);
reg [15:0]col_cnt;
wire odata_temp;

always@(posedge bit_clk or posedge reset_p)
begin
if(reset_p)
col_cnt <= 16'd0;
else if(col_cnt == COL_CNT-1)
col_cnt <= COL_CNT - 1'd1;
else
col_cnt <= col_cnt + 1'd1;
end

assign odata_temp_p = row_data[COL_CNT - 1 - col_cnt] ? bit1_roll_clk : 1'd1;
assign odata_temp_n = row_data[COL_CNT - 1 - col_cnt] ? 1'd1 : bit1_roll_clk;

assign odata = TURN ? odata_temp_n : odata_temp_p;

endmodule

`timescale 1ns/1ns

module sim_char_display();
wire [15:0]odata;
reg [63:0]data1_row[15:0];
reg [63:0]data2_row[15:0]