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原创 带使能端的寄存器（verilog设计）

分享一下带使能端的D触发器的设计module reg_A(Ain, Clock, R, Q);input wire Ain;input wire Clock;input wire [15:0] R;output reg [15:0] Q;initial Q =0;always@(posedge Clock) begin if(Ain == 1) Q <= R; else Q <= Q;