Makefile基础

Definitions

1. Targets: file names separated by spaces; typically one target per rule; the default target is the first target
2. Commands: series of steps typically used to make the target(s); start with a tab character
3. Prerequisites: also called “dependencies”; file names separated by spaces, need to exist before the commands for the target(s) are run
4. $@: an automatic variable that contains the target name

Wildcard

1. * wildcard search your filesystem for matching filenames.
   print: $(wildcard *.c)
2. * may be used in the target, prerequisites, or in the wildcard function, but may not be directly used in variable definitions. When * matches no files, it is left there as it is unless run in the wildcard function.

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3. When % is used in “matching” mode, it matches one or more characters in a string. This match is called the stem. When used in “replacing” mode, it takes the stem that was matched and replaces that in a string. % is most often used in rule definitions and in some specific functions.

Automatic Variables

1. $@. The file name of the target of the rule. If the target is an archive member, then $@ is the name of the archive file. In a pattern rule that has multiple targets, $@ is the name of whichever target caused the rule’s recipe to be run.
2. $?. The names of all the prerequisites that are newer than the target, with spaces between them. If the target does not exist, all prerequisites will be included. For prerequisites which are archive members, only the named member is used.
3. $^. The names of all the prerequisites, with spaces between them. For prerequisites which are archive members, only the named member is used.