Cortex-A7 MPCore Technical Reference Manual(Revision: r0p5)

TRM：Technical Reference Manual 

Preface

This book is for the Cortex-A7 MPCore processor. This is a multiprocessor device that has between one to four processors.

See Infocenter, http://infocenter.arm.com, for access to ARM documentation.这个网址可以下载ARM的文档。

Chapter 1 Introduction

Cortex-A7 MPCore processor：ARMv7-A architecture

The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor devi ce with a L1 cache subsystem, an  optional integrated GIC, and an optional L2 cache controller.

这个文档（Cortex-A7 MPCore Technical Reference Manual）只是对Cortex-A7 MPCore processor特性的介绍，对ARM通用的介绍，需要看如下文档：

(1). ARM architecture，see “ARM Architecture Reference Manual”，介绍ARM架构。

(2). Advanced Microcontroller Bus Architectures，see “AMBA AXI Protocol Specification” and “AMBA APB Protocol Specification”。

(3). Debug architecture，see “CoreSight Architecture Specification” and “ARM Architecture Reference Manual”。

(4). Generic Interrupt Controller architecture，see ARM Generic Interrupt Controller Architecture Specification .

(5). Generic Timer architecture，see ARM Architecture Reference Manual.

Chapter 2 Functional Description

概念：TLB（Translation lookaside buffer）是位于内存中的页表的cache，如果没有TLB，则每次取数据都需要两次访问内存，即查页表获得物理地址和取数据。即TLB也是一种cache，只是这个cache是用来缓存页表的。

2.1 总体介绍了 Cortex-A7 MPCore processor 的功能模块图。

很显然，除了中断控制器GIC之外，最核心的就是CPU以及Memory系统（TLB，Cache(L1 and L2)，Main Memory）等，同时还要注意几个Interface：Embedded Trace Macrocell(ETM) interface，APB interface，Interrupts，ACE master interface。

主要的components：

(1)Data Processing Unit

该单元包含了Processor的大多数程序可见的状态，例如通用寄存器，状态寄存器，控制寄存器。该功能模块解码并执行指令，对与ARM架构相关的寄存器中的数据进行操作。

DPU中的指令来自于Prefetch Unit (PFU)，DPU还执行通过DCU这个接口给Memeory系统传送或接收数据的指令，DCU管理所有的load和store操作。See Chapter 3 Programmers Model for more information.

(2)System control coprocessor

The system control coprocessor, CP15, provides configuration and control of the memory system and its associated functionality. See Chapter 4 System Control for more information.

(3)Instruction side  memory system

The instruction side memory system includes:
• Instruction Cache Unit.
• Prefetch Unit.

Instruction Cache Unit

包含Instruction Cache controller and its associated linefill buffer。The Cortex-A7 MPCore IC ache is two-way set associative and uses  Virtually Indexed Physically Tagged  (VIPT) cache-lines holding up  to 8 ARM or Thumb 32-bit 
instructions or up to 16 Thumb 16-bit instructions.

Prefetch Unit

The Prefetch Unit(PFU) 从instruction cache或者external memory中获取指令，并预测指令流中分支的走向，最后把指令传输给DPU来处理。在任何时刻，最多可达4条指令可被预取，2条可被传输给DPU。

PFU包含以下单元：Branch Target Instruction Cache ，Branch Target Address Cache，Branch prediction，Return stack 

(4)Data side memory system

This section describes the following:

• Data Cache Unit.
• Store Buffer.
• Bus Interface Unit and SCU interface.

Data Cache Unit

包括The Level 1(L1) data cache controller，The load/store pipeline，The system coprocessor controller，An interface to receive coherency requests from the Snoop Control Unit  (SCU).

Store Buffer

Bus Interface Unit and SCU interface

(5)L1 memory system

The processor L1 memory system  includes the foll owing features:
• Separate instruction and data caches.
• Export of memory attributes for system caches.

先看到这里。