[整理] How to calculate DECOUPLING CAPACITANCE

CURRENT consumption is constantly rising with increasing clock frequencies in modern VLSI circuits. The Power Delivery Network (PDN) is required to have a low-impedance resonant-free profile over a wide frequency range. This requirement is achieved by adding decoupling capacitances at the board, package, and die levels.

 The impedance at low frequencies is associated with board- level components, at middle frequencies with the package, and at high frequencies with on-die elements .

The purpose of decoupling capacitors is to provide local “filtering” of the power/ground at the device within a system. Filtering of the power/ground is needed due to “noise” that is induced in the power/ground system by the transient switching current generated by digital devices. The power/ground decoupling network should be designed to accommodate the transient “noise”.

Since an individual decoupling capacitor is effective at a specific range of frequencies centered at its resonant frequency, it is important that the resonant frequency be taken into account when choosing a capacitor. To cover a broad range of frequencies, a mixture of capacitor values should be used. For reference the capacitive reactance is defined by the following formula：
                                                “capacitor reactance = 1 / (2 * Pie * frequency) "

The duration of a single instruction execution in a processor clocked at 3 GHz with a pipe depth of 30 stages is "d = pipe_stages / f = 30 / (3*10) ^9 = 10 ns". which corresponds to a current frequency component of 100 MHz. Package decoupling capacitors, however, are typically effective up to 10-20MHz, so these capacitances cannot filter out the frequency component at 100 MHz. Hence, on-die decoupling capacitance is essential.