FPGA 使用verilog 编写的AD tlc549 测试程序，数码管做显示，本程序已验证

最新推荐文章于 2023-08-30 17:01:50 发布

fengdawei2014

最新推荐文章于 2023-08-30 17:01:50 发布

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CC 4.0 BY-SA版权

分类专栏： FPGA 文章标签： FPGA Verilog AD TLC5

本文链接：https://blog.youkuaiyun.com/fengdawei2014/article/details/39830657

该博客详细介绍了如何利用Verilog编写针对FPGA的AD TLC549测试程序，数码管显示转换结果。程序经过验证，适配了TLC548和TLC549的时钟频率限制，实现了高效率的数据采集和转换，通过数码管显示AD转换数据。

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/*
**author : fengdawei
**data : 2014/10/6
**description :
模块number_mod_module U5、smg_encoder_module U6、smg_scan_module U7、
row_scan_module U1、column_scan_module U2参照黑金数码管显示代码，用于显示
AD转换后的三位数值；
模块smg_check U4用于测试数码管正常显示；
模块ad_tlc549 U3用于AD处理，返回一个八位的数据，时序图具体参考TI官方资料
**此测试程序是为将ad数据存储到RAM和从RAM读走，测试ip核做准备。
*/
module experiment_ram(
clk,
rst,
//enable_ad,
ad_data,
row_scan_sig,
column_scan_sig,
ad_cs,
ad_clk
);

input clk;
input rst;

//input enable_ad;
input ad_data;

output [7:0] row_scan_sig;
output [2:0] column_scan_sig;
output ad_cs;
output ad_clk;

wire [7:0] smg_display_data;
ad_tlc549 U3
(
.clk(clk),
.rst(rst),
//.enable_ad(enable_ad),
.ad_data(ad_data),
.ad_cs(ad_cs),
.ad_clk(ad_clk),
.digit_data(smg_display_data)
);
/**/
/*
//smg_check模块用于测试数码管
wire [7:0] smg_display_data;
smg_check U4
(
.clk(clk),
.rst(rst),
.smg_display_data(smg_display_data)
);
*/
wire [3:0] hundred_data;
wire [3:0] ten_data;
wire [3:0] one_data;
number_mod_module U5
(
.clk(clk),
.rst(rst),
.number_data(smg_display_data),
.hundred_data(hundred_data),
.ten_data(ten_data),
.one_data(one_data)
);

wire [7:0] hundred_smg_data;
wire [7:0] ten_smg_data;
wire [7:0] one_smg_data;
smg_encoder_module U6
(
.clk(clk),
.rst(rst),
.hundred_data(hundred_data),
.ten_data(ten_data),
.one_data(one_data),
.hundred_smg_data(hundred_smg_data),
.ten_smg_data(ten_smg_data),
.one_smg_data(one_smg_data)
);

smg_scan_module U7
(
.clk(clk),
.rst(rst),
.hundred_smg_data(hundred_smg_data),
.ten_smg_data(ten_smg_data),//8'b1100_0000
.one_smg_data(one_smg_data),//8'b1100_0000
.row_scan_sig(row_scan_sig),
.column_scan_sig(column_scan_sig)
);

endmodule

/*
***The maximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz,
and the I/O CLOCK input frequency of theTLC549 is specified up to 1.1 MHz.
***the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHz
and requires no external components.
***Conversion Time...17 μs Max
***NOTES: A. The conversion cycle, which requires 36 internal system clock periods (17 μs maximum),
is initiated with the eighth I/O clock pulse trailing edge after CS goes low for the
channel whose address exists in memory at the time.
B. The most significant bit (A7) is automatically placed on the DATA OUT bus after CS is
brought low. The remaining seven bits (A6–A0) are clocked out on the first seven I/O