freescale usb wakeup的中断号是怎样来的

本文详细解析了Linux内核中USB-Wakeup模块的初始化过程,包括设备注册、IRQ分配等关键步骤,并追溯了相关配置数据的来源。

1. arch/arm/plat-mxc/usb_wakeup.c

<span style="font-size:18px;">243 static struct platform_driver wakeup_d = {
244     .probe   = wakeup_dev_probe,
245     .remove  = wakeup_dev_exit,
246     .driver = {
247         .name = "usb-wakeup",
248     },
249 };
250 
251 static int __init wakeup_dev_init(void)
252 {
253     return platform_driver_register(&wakeup_d);
254 }
</span>
注册了一个叫usb-wakeup的driver, 这个设备是在哪里被add到系统的呢?

2. arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c

这个文件中有个函数

<span style="font-size:18px;"> 36 struct platform_device *__init imx_add_fsl_usb2_wakeup(
 37         const struct imx_fsl_usb2_wakeup_data *data,
 38         const struct fsl_usb2_wakeup_platform_data *pdata)
 39 {
 40     struct resource res[] = {
 41         {
 42             .start = data->irq_phy,
 43             .end = data->irq_phy,
 44             .flags = IORESOURCE_IRQ,
 45         }, {
 46             .start = data->irq_core,</span>
<span style="font-size:18px;"> 47<span style="white-space:pre">		</span>.end = data->irq_core,
 48             .flags = IORESOURCE_IRQ,
 49         },
 50     };
 51     return imx_add_platform_device_dmamask("usb-wakeup", data->id,
 52             res, ARRAY_SIZE(res),
 53             pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 54 }
</span>
在这个函数里面可以看到usb-wakeup这个设备被add了,问题是这个函数又在哪里被调用呢?

3. arch/arm/mach-mx6/devices-imx6q.h

找啊找,找到了这里

97 #define imx6sl_add_fsl_usb2_hs_wakeup(id, pdata)    \
 98     imx_add_fsl_usb2_wakeup(&imx6sl_fsl_hs_wakeup_data[id - 1], pdata)
 99 

现在变成了找imx6sl_add_fsl_usb2_hs_wakeup在哪里被调用了。

4.arch/arm/mach-mx6/usb_h1.c


<span style="font-size:18px;">static int  __init mx6_usb_h1_init(void)
421 {
......
465     if (cpu_is_mx6sl())
466         pdev_wakeup = imx6sl_add_fsl_usb2_hs_wakeup(1, &usbh1_wakeup_config);
467     else
468         pdev_wakeup = imx6q_add_fsl_usb2_hs_wakeup(1, &usbh1_wakeup_config);
469     platform_device_add(pdev);//其实这个pdev的name也是“usb-wakeup”,但是为什么pdev的platform_data是在下面赋值呢?为什么前面</span><span style="font-size: 18px; font-family: Arial, Helvetica, sans-serif;">imx_add_platform_device_dmamask已经调用过platform_device_add,这里还要这样调用呢?</span><span style="font-size:18px;">
470     ((struct fsl_usb2_platform_data *)(pdev->dev.platform_data))->wakeup_pdata =
471         (struct fsl_usb2_wakeup_platform_data *)(pdev_wakeup->dev.platform_data);
472     return 0;
473 }
474 module_init(mx6_usb_h1_init);</span>
就这样在开机时被注册了。

回到题目: 要找irq是从哪来了

先回到文件 arch/arm/plat-mxc/usb_wakeup.c看函数

 static int wakeup_dev_probe(struct platform_device *pdev){
.....
205     ctrl->wakeup_irq = platform_get_irq(pdev, 1);//这里就是irq的由来
206     ctrl->usb_irq = platform_get_irq(pdev, 1);
207     ctrl->thread_close = false;
208     if (ctrl->wakeup_irq != ctrl->usb_irq)
209         interrupt_flag = IRQF_DISABLED;
210     else
211         interrupt_flag = IRQF_SHARED;
212     status = request_irq(ctrl->wakeup_irq, usb_wakeup_handler, interrupt_flag, "usb_wakeup", (void *)ctrl);
213     if (status)
214         goto error1;
215 
....
}
platform_get_irq(pdev, 1);返回的其实是
<pre name="code" class="html">60 int platform_get_irq(struct platform_device *dev, unsigned int num)
  61 {
  62     struct resource *r = platform_get_resource(dev, IORESOURCE_IRQ, num);
  63 
  64     return r ? r->start : -ENXIO;
  65 }



所以这个irq是在imx_add_fsl_usb2_wakeup中被赋值的。

这个会从imx_fsl_usb2_wakeup_data里面找,这东西又在哪里被赋值呢?

 arch/arm/mach-mx6/devices-imx6q.h中需要imx6q_fsl_hs_wakeup_data[id - 1],这个东西

会在arch/arm/mach-mx6/usb_h1.c文件的函数 mx6_usb_h1_init被赋值为struct imx_fsl_usb2_wakeup_data imx6q_fsl_hs_wakeup_data[] = {

        imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 1, HS1)};

最终会变成

arch/arm/mach-mx6/usb.h: .irq_phy = soc ## _INT_USB_PHY ## _id, \
arch/arm/plat-mxc/include/mach/mx6.h:#define MX6Q_INT_USB_PHY0 76

/* * Copyright (C) 2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include <dt-bindings/input/input.h> #include "imx6ull.dtsi" / { model = "Freescale i.MX6 ULL 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; chosen { stdout-path = &uart1; }; memory { reg = <0x80000000 0x20000000>; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; linux,cma { compatible = "shared-dma-pool"; reusable; size = <0x8000000>; linux,cma-default; }; }; backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; status = "okay"; }; pxp_v4l2 { compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; status = "okay"; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_can_3v3: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "can-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; reg_sd1_vmmc: regulator@1 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; /* gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; */ enable-active-high; }; reg_vref_adc: regulator@2 { compatible = "regulator-fixed"; regulator-name = "VREF_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; reg_gpio_dvfs: regulator-gpio { compatible = "regulator-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dvfs>; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1400000>; regulator-name = "gpio_dvfs"; regulator-type = "voltage"; gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; states = <1300000 0x1 1400000 0x0>; }; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds &pinctrl_beep>; led1{ label = "sys-led"; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; default-state = "on"; }; beep{ label = "beep"; gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; gpio_keys: gpio_keys@0 { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; #address-cells = <1>; #size-cells = <0>; autorepeat; key1@1 { label = "USER-KEY1"; linux,code = <114>; gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; gpio-key,wakeup; }; }; sound { /*compatible = "fsl,imx6ul-evk-wm8960", "fsl,imx-audio-wm8960"; model = "wm8960-audio"; cpu-dai = <&sai2>; audio-codec = <&codec>; asrc-controller = <&asrc>; codec-master; gpr = <&gpr 4 0x100000 0x100000>; /* * hp-det = <hp-det-pin hp-det-polarity>; * hp-det-pin: JD1 JD2 or JD3 * hp-det-polarity = 0: hp detect high for headphone * hp-det-polarity = 1: hp detect high for speaker */ hp-det = <3 0>; /* hp-det-gpios = <&gpio5 4 0>; mic-det-gpios = <&gpio5 4 0>; */ /*audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", "Ext Spk", "SPK_RP", "Ext Spk", "SPK_RN", "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", "RINPUT1", "Main MIC", "RINPUT2", "Main MIC", "Mic Jack", "MICB", "Main MIC", "MICB", "CPU-Playback", "ASRC-Playback", "Playback", "CPU-Playback", "ASRC-Capture", "CPU-Capture", "CPU-Capture", "Capture";*/ status = "disabled"; }; spi4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; /*pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; */ status = "okay"; gpio-sck = <&gpio5 11 0>; gpio-mosi = <&gpio5 10 0>; /*cs-gpios = <&gpio5 7 0>; */ num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; gpio_spi: gpio_spi@0 { compatible = "fairchild,74hc595"; gpio-controller; #gpio-cells = <2>; reg = <0>; registers-number = <1>; registers-default = /bits/ 8 <0x57>; spi-max-frequency = <100000>; }; }; /*sii902x_reset: sii902x-reset { compatible = "gpio-reset"; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; reset-delay-us = <100000>; #reset-cells = <0>; status = "disabled"; };*/ /*liu_devices*/ alphaled { compatible = "imx6ull,alphaled"; #address-cells = <1>; #size-cells = <1>; status = "okay"; reg = < 0X020C406C 0x04 0X020E0068 0x04 0X020E02F4 0x04 0X0209C000 0x04 0X0209C004 0x04>; }; sr501@0 { compatible = "imx6ull,sr501"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sr501>; irq-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; label = "sr501_pir"; interrupt-parent = <&gpio5>; interrupts = <7 IRQ_TYPE_EDGE_RISING>; }; sr04@0 { compatible = "imx6ull,sr04"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sr04>; trig-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; echo-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; status = "okay"; }; stepmotor_28byj@0 { compatible = "imx6ull,motor"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_motor>; gpios = <&gpio1 27 GPIO_ACTIVE_HIGH &gpio1 25 GPIO_ACTIVE_HIGH &gpio1 26 GPIO_ACTIVE_HIGH &gpio1 24 GPIO_ACTIVE_HIGH>; status = "okay"; }; dht11@0 { compatible = "imx6ull,dht11"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dht11>; data-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; label = "dht11-sensor"; status = "okay"; }; sg90@0 { compatible = "imx6ull,sg90"; /* 驱动匹配标识 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; /* 关联PWM3的引脚配置 */ pwm-names = "sg90_pwm"; /* PWM名称(驱动中引用) */ /* pwms = <PWM控制器 通道号 周期(ns)>:通道0(IMX6ULL每个PWM仅1通道),周期20ms */ pwms = <&pwm3 0 20000000>; label = "sg90-servo"; /* 调试标签 */ status = "okay"; }; irda_receiver@0 { compatible = "imx6ull,irda"; // 与驱动的of_match_table严格一致(含空格) irda-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; // 红外接收管OUT引脚:GPIO1_IO04,低电平有效 pinctrl-names = "default"; pinctrl-0 = <&pinctrl_irda>; // 绑定引脚配置(避免GPIO被其他设备占用) status = "okay"; }; }; &cpu0 { arm-supply = <&reg_arm>; soc-supply = <&reg_soc>; dc-supply = <&reg_gpio_dvfs>; }; &clks { assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <722534400>; }; &csi { status = "disabled"; /*port { csi1_ep: endpoint { remote-endpoint = <&ov5640_ep>; }; };*/ }; &ecspi3 { fsl,spi-num-chipselects = <1>; /*cs-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "disabled"; spidev: icm20608@0 { compatible = "alientek,icm20608"; spi-max-frequency = <8000000>; reg = <0>; }; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1 &pinctrl_fec1_reset>; phy-mode = "rmii"; phy-handle = <&ethphy0>; /*phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; */ phy-reset-duration = <200>; status = "okay"; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2 &pinctrl_fec2_reset>; phy-mode = "rmii"; phy-handle = <&ethphy1>; phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; phy-reset-duration = <200>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <&reg_can_3v3>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <&reg_can_3v3>; status = "disabled"; }; &gpc { fsl,cpu_pupscr_sw2iso = <0x1>; fsl,cpu_pupscr_sw = <0x0>; fsl,cpu_pdnscr_iso2sw = <0x1>; fsl,cpu_pdnscr_iso = <0x1>; fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ }; &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; mag3110@0e { compatible = "fsl,mag3110"; reg = <0x0e>; position = <2>; }; ap3216c@1e { compatible = "ap3216c"; reg = <0x1e>; }; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; /*codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; wlf,shared-lrclk; }; ov5640: ov5640@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi1 &csi_pwn_rst>; clocks = <&clks IMX6UL_CLK_CSI>; clock-names = "csi_mclk"; pwn-gpios = <&gpio1 4 1>; rst-gpios = <&gpio1 2 0>; csi_id = <0>; mclk = <24000000>; mclk_source = <0>; status = "okay"; port { ov5640_ep: endpoint { remote-endpoint = <&csi1_ep>; }; }; };*/ edt-ft5x06@38 { compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; pinctrl-names = "default"; pinctrl-0 = <&ts_int_pin &ts_reset_pin>; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; status = "okay"; }; /*goodix_ts@5d { compatible = "goodix,gt9xx"; reg = <0x5d>; status = "okay"; interrupt-parent = <&gpio1>; interrupts = <9 0>; pinctrl-0 = <&ts_int_pin &ts_reset_pin>; goodix,rst-gpio = <&gpio5 9 GPIO_ACTIVE_LOW>; goodix,irq-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; };*/ /* sii902x: sii902x@39 { compatible = "SiI,sii902x"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sii902x>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; mode_str = "1280x720M@60"; bits-per-pixel = <16>; resets = <&sii902x_reset>; reg = <0x39>; status = "disabled"; };*/ }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx6ul-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x13058 /* USB_OTG1_ID */ >; }; pinctrl_motor: motorgrp { fsl,pins = < MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 >; }; pinctrl_sr501: sr501grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 /* 空闲引脚 */ >; }; pinctrl_sr04: sr04grp { fsl,pins = < MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x10b0 MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x10b0 >; }; pinctrl_dht11: dht11grp { fsl,pins = < /* 启用上拉(DHT11必需) */ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x1b010 >; }; pinctrl_pwm3: pwm3grp { fsl,pins = < MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x10b0 >; }; pinctrl_adc1: adc1grp { fsl,pins = < /*MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0*/ >; }; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b008 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b008 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b008 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b008 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b008 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b008 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b008 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b008 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b008 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b008 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b008 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b008 >; }; pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 >; }; pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 >; }; pinctrl_ecspi3: ecspi3grp { fsl,pins = < /*MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 MISO MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 MOSI MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 CLK MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x100b0 CS */ >; }; pinctrl_gpio_leds: gpio-leds { fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 >; }; pinctrl_gpio_keys: gpio-keys { fsl,pins = < MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x80000000 >; }; pinctrl_flexcan1: flexcan1grp{ fsl,pins = < /* MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 */ >; }; pinctrl_flexcan2: flexcan2grp{ fsl,pins = < /* MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 */ >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 >; }; pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x49 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x49 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x49 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x49 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x49 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x49 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x49 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x51 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x49 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x49 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x49 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x49 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x49 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x49 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x49 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x51 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x49 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x49 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x49 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x49 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x49 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x49 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x49 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x51 >; }; pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x49 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x49 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x49 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x49 >; }; pinctrl_pwm1: pwm1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 >; }; pinctrl_qspi: qspigrp { fsl,pins = < MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; }; pinctrl_sai2: sai2grp { fsl,pins = < /*MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088*/ >; }; pinctrl_sii902x: hdmigrp-1 { fsl,pins = < MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11 >; }; pinctrl_tsc: tscgrp { fsl,pins = < /*MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 */ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < /*MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1*/ >; }; pinctrl_uart2dte: uart2dtegrp { fsl,pins = < /*MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1*/ >; }; pinctrl_uart3: uart3grp { fsl,pins = < /*MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1*/ >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; }; pinctrl_usdhc2_8bit: usdhc2grp_8bit { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 >; }; pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 >; }; pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; ts_int_pin: ts_int_pin_mux { fsl,pins = < MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x49 >; }; csi_pwn_rst: csi_pwn_rstgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /*MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0*/ >; }; }; }; &iomuxc_snvs { pinctrl-names = "default_snvs"; pinctrl-0 = <&pinctrl_hog_2>; imx6ul-evk { pinctrl_hog_2: hoggrp-2 { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 >; }; pinctrl_dvfs: dvfsgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 >; }; pinctrl_lcdif_reset: lcdifresetgrp { fsl,pins = < /* used for lcd reset */ /*MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49 */ >; }; pinctrl_spi4: spi4grp { fsl,pins = < MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 >; }; pinctrl_fec1_reset: fec1_resetgrp { fsl,pins = < /*MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79 */ >; }; pinctrl_fec2_reset: fec2_resetgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x79 >; }; pinctrl_sai2_hp_det_b: sai2_hp_det_grp { fsl,pins = < /*MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 */ >; }; ts_reset_pin: ts_reset_pin_mux { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49 >; }; pinctrl_beep: beep { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 >; }; pinctrl_irda: irdagrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b088 // 输入模式+上拉 >; }; }; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; display = <&display0>; status = "okay"; display0: display { bits-per-pixel = <16>; bus-width = <24>; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <35500000>; hactive = <800>; vactive = <480>; hfront-porch = <210>; hback-porch = <46>; hsync-len = <20>; vback-porch = <23>; vfront-porch = <22>; vsync-len = <3>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; /* rgb to hdmi: pixelclk-ative should be set to 1 */ pixelclk-active = <0>; }; }; }; }; &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm3 { clock-names = "ipg", "per"; clocks = <&clks IMX6UL_CLK_PWM3>, <&clks IMX6UL_CLK_PWM3>; status = "okay"; }; &adc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; num-channels = <2>; vref-supply = <&reg_vref_adc>; status = "okay"; }; &pxp { status = "okay"; }; &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; ddrsmp=<0>; flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a"; spi-max-frequency = <29000000>; spi-nor,ddr-quad-read-dummy = <6>; reg = <0>; }; }; &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2 &pinctrl_sai2_hp_det_b>; assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, <&clks IMX6UL_CLK_SAI2>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <11289600>; status = "disabled"; }; /* &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xfff>; status = "disabled"; }; */ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; fsl,uart-has-rtscts; /* for DTE mode, add below change */ /* fsl,dte-mode; */ /* pinctrl-0 = <&pinctrl_uart2dte>; */ status = "disabled"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "disabled"; }; &usbotg1 { dr_mode = "otg"; srp-disable; hnp-disable; adp-disable; status = "okay"; }; &usbotg2 { dr_mode = "host"; disable-over-current; status = "okay"; }; &usbphy1 { tx-d-cal = <0x5>; }; &usbphy2 { tx-d-cal = <0x5>; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; keep-power-in-suspend; enable-sdio-wakeup; vmmc-supply = <&reg_sd1_vmmc>; no-1-8-v; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; non-removable; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,wdog_b; }; 我的设备树无法触屏
最新发布
09-10
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