ECE 525.642 FPGA Design using VHDL Lab 7 R

Java Python Lab 7 Assignment

ECE 525.642 FPGA Design using VHDL

Sine Wave Generator using Xilinx IP

The goal of this lab is to understand how intellectual property (IP) from various vendors can be used and incorporated into your own projects.  This lab will utilize the Sine look-up table that will be generated from the Xilinx Vivado IP catalog’s DDS compiler.

This project involves designing a sine wave tone generator.  The design will use the slider switches to set the tone frequency whereas a different set of switches will be used to set the volume of the sine waveform.  One way to implement the tone generator is shown in the following block diagram, however, you can use different approaches.  Either way, make sure to document your block diagram!

The switches are used to set the sample rate generator.  This signal is an enable pulse with a specific period which is used to increment an 8-bit phase counter. The phase counter is then used as the input   to a sine LUT DDS component that is generated using the Xilinx Vivado IP catalog’s DDS compiler. The output of the Sine LUT is a 16-bit value that is then passed into a volume level shifter which is controlled using another set of slider switches. The shifted sine wave is then bound to the input of a PWM generator, from which the output is used to drive the mono audio-output.

Figure 1 - Lab 7 Block Diagram

All of the white blocks will be process blocks or entity/architecture pairs created by the designer, while the orange block is a piece of IP that will be generated by Xilinx Vivado and used in the design.

This lab has the following requirements:

•    BTNC is the overall reset for all sequential logic

•    SW(5:3) will be used to set the volume level of the output

o ‘111’ will be maximum volume

o ‘000’ will be minimum volume

o All the values in between will be shifted based on switch positions. (see below)

•    SW(2:0) will be used to set the output frequency of the sine wave

o ‘000’ will be 0Hz or DC **special case for counter!

o ‘001’ will be 500Hz

o ‘010’ will be 1000Hz

o ‘011’ will be 1500Hz

o ‘100’ will be 2000Hz

o ‘101’ will be 2500Hz

o ‘110’ will be 3000Hz

o ‘111’ will be 3500Hz

•    SW(15) will be used to turn on and o