//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// otherwise provided in a valid license issued to you by
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// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : UltraScale+ FPGA PCI Express v4.0 Integrated Block
// File : cgator_wrapper.v
// Version : 1.3
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
// Project : Ultrascale FPGA Gen4 Integrated Block for PCI Express
// File : cgator_wrapper.v
// Version : 1.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
(* DowngradeIPIdentifiedWarnings = "yes" *)
module cgator_wrapper
#(
// Configurator parameters
parameter PCIE_LOCATION = "X0Y0",
parameter TCQ = 1,
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "TRUE",
parameter PIPE_SIM_MODE = "FALSE",
parameter EXTRA_PIPELINE = 1,
parameter ROM_FILE = "cgator_cfg_rom.data",
parameter ROM_SIZE = 32,
parameter [15:0] REQUESTER_ID = 16'h10EE,
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking Module
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4, // 1- GEN1, 2 - GEN2, 4 - GEN3
parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h8, // 1- X1, 2 - X2, 4 - X4, 8 - X8
parameter PL_DISABLE_EI_INFER_IN_L0 = "TRUE",
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE",
// USER_CLK[1/2]_FREQ :[0] = Disable user clock; [1] = 31.25 MHz; [2] = 62.50 MHz (default); [3] = 125.00 MHz; [4] = 250.00 MHz; [5] = 500.00 MHz;
parameter integer USER_CLK2_FREQ = 2,
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter AXISTEN_IF_RQ_PARITY_CHECK = "FALSE",
parameter AXI4_CQ_TUSER_WIDTH = 88,
parameter AXI4_CC_TUSER_WIDTH = 33,
parameter AXI4_RQ_TUSER_WIDTH = 62,
parameter AXI4_RC_TUSER_WIDTH = 75,
parameter C_DATA_WIDTH = 64,
parameter KEEP_WIDTH = C_DATA_WIDTH / 32
)
(
//-------------------------------------------------------
// 0. Configurator I/Os
//-------------------------------------------------------
input start_config,
output finished_config,
output failed_config,
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_txp,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_txn,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_rxp,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_rxn,
//-------------------------------------------------------
// 2. Transaction (AXIS) Interface
//-------------------------------------------------------
output user_clk_out,
output user_reset_out,
output user_lnk_up,
output phy_rdy_out,
//-------------------------------------------------------
output s_axis_rq_tready,
input [C_DATA_WIDTH-1:0] s_axis_rq_tdata,
input [KEEP_WIDTH-1:0] s_axis_rq_tkeep,
input [AXI4_RQ_TUSER_WIDTH-1:0] s_axis_rq_tuser,
input s_axis_rq_tlast,
input s_axis_rq_tvalid,
//-------------------------------------------------------
output [C_DATA_WIDTH-1:0] m_axis_rc_tdata,
output [KEEP_WIDTH-1:0] m_axis_rc_tkeep,
output m_axis_rc_tlast,
output m_axis_rc_tvalid,
output [AXI4_RC_TUSER_WIDTH-1:0] m_axis_rc_tuser,
input m_axis_rc_tready,
//-------------------------------------------------------
output wire [C_DATA_WIDTH-1:0] m_axis_cq_tdata,
output wire [AXI4_CQ_TUSER_WIDTH-1:0] m_axis_cq_tuser,
output wire m_axis_cq_tlast,
output wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep,
output wire m_axis_cq_tvalid,
input m_axis_cq_tready,
//-------------------------------------------------------
input [C_DATA_WIDTH-1:0] s_axis_cc_tdata,
input [AXI4_CC_TUSER_WIDTH-1:0] s_axis_cc_tuser,
input s_axis_cc_tlast,
input [KEEP_WIDTH-1:0] s_axis_cc_tkeep,
input s_axis_cc_tvalid,
output wire [3:0] s_axis_cc_tready,
//-------------------------------------------------------
// 3. Configuration (CFG) Interface - EP and RP
//-------------------------------------------------------
output [3:0] pcie_tfc_nph_av,
output [3:0] pcie_tfc_npd_av,
//-------------------------------------------------------
// Error Reporting Interface
//-------------------------------------------------------
output wire [5:0] pcie_rq_seq_num0,
output wire pcie_rq_seq_num_vld0,
output wire [5:0] pcie_rq_seq_num1,
output wire pcie_rq_seq_num_vld1,
output wire [7:0] pcie_rq_tag0,
output wire pcie_rq_tag_vld0,
output wire [7:0] pcie_rq_tag1,
output wire pcie_rq_tag_vld1,
output wire [3:0] pcie_rq_tag_av,
input [1:0] pcie_cq_np_req,
output [5:0] pcie_cq_np_req_count,
output cfg_phy_link_down,
output [1:0] cfg_phy_link_status,
output [2:0] cfg_negotiated_width,
output [1:0] cfg_current_speed,
output [1:0] cfg_max_payload,
output [2:0] cfg_max_read_req,
output [15:0] cfg_function_status,
output [11:0] cfg_function_power_state,
output [503:0] cfg_vf_status,
output [755:0] cfg_vf_power_state,
output [1:0] cfg_link_power_state,
output cfg_err_cor_out,
output cfg_err_nonfatal_out,
output cfg_err_fatal_out,
output [4:0] cfg_local_error_out,
output cfg_local_error_valid,
output [5:0] cfg_ltssm_state,
output [1:0] cfg_rx_pm_state,
output [1:0] cfg_tx_pm_state,
output [3:0] cfg_rcb_status,
output [1:0] cfg_obff_enable,
output cfg_pl_status_change,
output [3:0] cfg_tph_requester_enable,
output [11:0] cfg_tph_st_mode,
output [251:0] cfg_vf_tph_requester_enable,
output [755:0] cfg_vf_tph_st_mode,
//-------------------------------------------------------
// Interrupt Interface Signals
//-------------------------------------------------------
input [3:0] cfg_interrupt_int,
input [1:0] cfg_interrupt_pending,
output cfg_interrupt_sent,
output [3:0] cfg_interrupt_msi_enable,
output [11:0] cfg_interrupt_msi_mmenable,
output cfg_interrupt_msi_mask_update,
output [31:0] cfg_interrupt_msi_data,
input [1:0] cfg_interrupt_msi_select,
input [31:0] cfg_interrupt_msi_int,
input [63:0] cfg_interrupt_msi_pending_status,
output cfg_interrupt_msi_sent,
output cfg_interrupt_msi_fail,
input [2:0] cfg_interrupt_msi_attr,
input cfg_interrupt_msi_tph_present,
input [1:0] cfg_interrupt_msi_tph_type,
input [7:0] cfg_interrupt_msi_tph_st_tag,
input cfg_interrupt_msi_pending_status_data_enable,
input [3:0] cfg_interrupt_msi_pending_status_function_num,
input [2:0] cfg_interrupt_msi_function_number,
//-------------------------------------------------------
input sys_clk,
input sys_clk_gt,
input sys_reset_n
//-------------------------------------------------------
);
//--------------------------------------------------------------------------------------------------------------------//
// Connections between Root Port and Configurator
//--------------------------------------------------------------------------------------------------------------------//
wire [3:0] rport_s_axis_rq_tready;
wire [C_DATA_WIDTH-1:0] rport_s_axis_rq_tdata;
wire [KEEP_WIDTH-1:0] rport_s_axis_rq_tkeep;
wire [AXI4_RQ_TUSER_WIDTH-1:0] rport_s_axis_rq_tuser;
wire rport_s_axis_rq_tlast;
wire rport_s_axis_rq_tvalid;
wire [C_DATA_WIDTH-1:0] rport_m_axis_rc_tdata;
wire [KEEP_WIDTH-1:0] rport_m_axis_rc_tkeep;
wire rport_m_axis_rc_tlast;
wire rport_m_axis_rc_tvalid;
wire rport_m_axis_rc_tready;
wire [AXI4_RC_TUSER_WIDTH-1:0] rport_m_axis_rc_tuser;
// wire cfg_msg_received;
// wire [7 : 0] cfg_msg_received_data;
// wire [4 : 0] cfg_msg_received_type;
// ila_32 ila_cgator_0 (
// .clk(user_clk_out),
// .probe0({
// cfg_msg_received,
// cfg_msg_received_data,
// cfg_msg_received_type
// })
// );
//---------------------------------------------------------------------------------------//
// Core Top Level Wrapper
generate
if (PCIE_LOCATION == "X0Y0") begin
pcie4_uscale_plus_0 pcie4_uscale_plus_0_i (
//---------------------------------------------------------------------------------------//
// PCI Express (pci_exp) Interface //
//---------------------------------------------------------------------------------------//
//---------------------------------------------------------------------------------------//
// PCI Express (pci_exp) Interface //
//---------------------------------------------------------------------------------------//
// Tx
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
// Rx
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//---------------------------------------------------------------------------------------//
// AXI Interface //
//---------------------------------------------------------------------------------------//
.user_clk ( user_clk_out ),
.user_reset ( user_reset_out ),
.user_lnk_up ( user_lnk_up ),
.phy_rdy_out ( phy_rdy_out ),
.s_axis_rq_tlast ( rport_s_axis_rq_tlast ),
.s_axis_rq_tdata ( rport_s_axis_rq_tdata ),
.s_axis_rq_tuser ( rport_s_axis_rq_tuser ),
.s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ),
.s_axis_rq_tready ( rport_s_axis_rq_tready ),
.s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ),
.m_axis_rc_tdata ( rport_m_axis_rc_tdata ),
.m_axis_rc_tuser ( rport_m_axis_rc_tuser ),
.m_axis_rc_tlast ( rport_m_axis_rc_tlast ),
.m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ),
.m_axis_rc_tready ( rport_m_axis_rc_tready ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( m_axis_cq_tready ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------------------------//
// Configuration (CFG) Interface //
//---------------------------------------------------------------------------------------//
.pcie_tfc_nph_av ( pcie_tfc_nph_av ),
.pcie_tfc_npd_av ( pcie_tfc_npd_av ),
.pcie_rq_seq_num0 ( pcie_rq_seq_num0) ,
.pcie_rq_seq_num_vld0 ( pcie_rq_seq_num_vld0) ,
.pcie_rq_seq_num1 ( pcie_rq_seq_num1) ,
.pcie_rq_seq_num_vld1 ( pcie_rq_seq_num_vld1) ,
.pcie_rq_tag0 ( pcie_rq_tag0) ,
.pcie_rq_tag1 ( pcie_rq_tag1) ,
.pcie_rq_tag_av ( pcie_rq_tag_av) ,
.pcie_rq_tag_vld0 ( pcie_rq_tag_vld0) ,
.pcie_rq_tag_vld1 ( pcie_rq_tag_vld1) ,
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_local_error_out ( cfg_local_error_out ),
.cfg_local_error_valid ( cfg_local_error_valid ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rx_pm_state ( cfg_rx_pm_state ),
.cfg_tx_pm_state ( cfg_tx_pm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
// /* agan add @ 20220603, for debug*/
// .cfg_msg_received ( cfg_msg_received ) ,
// .cfg_msg_received_data ( cfg_msg_received_data ),
// .cfg_msg_received_type ( cfg_msg_received_type ),
// //
//-------------------------------------------------------------------------------//
// EP Only //
//-------------------------------------------------------------------------------//
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( {2'b0,cfg_interrupt_pending} ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status [31:0]),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_pending_status_function_num (2'b0),
.cfg_interrupt_msi_pending_status_data_enable (1'b0),
.cfg_interrupt_msi_function_number (8'b0 ),
//--------------------------------------------------------------------------------------//
// System(SYS) Interface //
//--------------------------------------------------------------------------------------//
.sys_clk ( sys_clk ),
.sys_clk_gt ( sys_clk_gt ),
.sys_reset ( sys_reset_n )
);
end
else if (PCIE_LOCATION == "X0Y1") begin
pcie4_uscale_plus_1 pcie4_uscale_plus_0_i (
//---------------------------------------------------------------------------------------//
// PCI Express (pci_exp) Interface //
//---------------------------------------------------------------------------------------//
//---------------------------------------------------------------------------------------//
// PCI Express (pci_exp) Interface //
//---------------------------------------------------------------------------------------//
// Tx
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
// Rx
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//---------------------------------------------------------------------------------------//
// AXI Interface //
//---------------------------------------------------------------------------------------//
.user_clk ( user_clk_out ),
.user_reset ( user_reset_out ),
.user_lnk_up ( user_lnk_up ),
.phy_rdy_out ( phy_rdy_out ),
.s_axis_rq_tlast ( rport_s_axis_rq_tlast ),
.s_axis_rq_tdata ( rport_s_axis_rq_tdata ),
.s_axis_rq_tuser ( rport_s_axis_rq_tuser ),
.s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ),
.s_axis_rq_tready ( rport_s_axis_rq_tready ),
.s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ),
.m_axis_rc_tdata ( rport_m_axis_rc_tdata ),
.m_axis_rc_tuser ( rport_m_axis_rc_tuser ),
.m_axis_rc_tlast ( rport_m_axis_rc_tlast ),
.m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ),
.m_axis_rc_tready ( rport_m_axis_rc_tready ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( m_axis_cq_tready ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------------------------//
// Configuration (CFG) Interface //
//---------------------------------------------------------------------------------------//
.pcie_tfc_nph_av ( pcie_tfc_nph_av ),
.pcie_tfc_npd_av ( pcie_tfc_npd_av ),
.pcie_rq_seq_num0 ( pcie_rq_seq_num0) ,
.pcie_rq_seq_num_vld0 ( pcie_rq_seq_num_vld0) ,
.pcie_rq_seq_num1 ( pcie_rq_seq_num1) ,
.pcie_rq_seq_num_vld1 ( pcie_rq_seq_num_vld1) ,
.pcie_rq_tag0 ( pcie_rq_tag0) ,
.pcie_rq_tag1 ( pcie_rq_tag1) ,
.pcie_rq_tag_av ( pcie_rq_tag_av) ,
.pcie_rq_tag_vld0 ( pcie_rq_tag_vld0) ,
.pcie_rq_tag_vld1 ( pcie_rq_tag_vld1) ,
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_local_error_out ( cfg_local_error_out ),
.cfg_local_error_valid ( cfg_local_error_valid ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rx_pm_state ( cfg_rx_pm_state ),
.cfg_tx_pm_state ( cfg_tx_pm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
// /* agan add @ 20220603, for debug*/
// .cfg_msg_received ( cfg_msg_received ) ,
// .cfg_msg_received_data ( cfg_msg_received_data ),
// .cfg_msg_received_type ( cfg_msg_received_type ),
// //
//-------------------------------------------------------------------------------//
// EP Only //
//-------------------------------------------------------------------------------//
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( {2'b0,cfg_interrupt_pending} ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status [31:0]),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_pending_status_function_num (2'b0),
.cfg_interrupt_msi_pending_status_data_enable (1'b0),
.cfg_interrupt_msi_function_number (8'b0 ),
//--------------------------------------------------------------------------------------//
// System(SYS) Interface //
//--------------------------------------------------------------------------------------//
.sys_clk ( sys_clk ),
.sys_clk_gt ( sys_clk_gt ),
.sys_reset ( sys_reset_n )
);
end
endgenerate
// IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_reset_n));
//IBUFDS_GTE3 refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n));
//--------------------------------------------------------------------------------------------------------------------//
// Instantiate Configurator design
//--------------------------------------------------------------------------------------------------------------------//
cgator #(
.TCQ ( TCQ ),
.AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE),
.EXTRA_PIPELINE ( EXTRA_PIPELINE ),
.ROM_SIZE ( ROM_SIZE ),
.ROM_FILE ( ROM_FILE ),
.REQUESTER_ID ( REQUESTER_ID ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.KEEP_WIDTH ( KEEP_WIDTH )
) cgator_i
(
// globals
.user_clk ( user_clk_out ),
.reset ( user_reset_out ),
// User interface for configuration
.start_config ( start_config ),
.finished_config ( finished_config ),
.failed_config ( failed_config ),
// Rport AXIS interfaces
.rport_s_axis_rq_tready ( rport_s_axis_rq_tready[0]),
.rport_s_axis_rq_tdata ( rport_s_axis_rq_tdata ),
.rport_s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ),
.rport_s_axis_rq_tuser ( rport_s_axis_rq_tuser ),
.rport_s_axis_rq_tlast ( rport_s_axis_rq_tlast ),
.rport_s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ),
.rport_m_axis_rc_tdata ( rport_m_axis_rc_tdata ),
.rport_m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ),
.rport_m_axis_rc_tlast ( rport_m_axis_rc_tlast ),
.rport_m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ),
.rport_m_axis_rc_tready ( rport_m_axis_rc_tready ),
.rport_m_axis_rc_tuser ( rport_m_axis_rc_tuser ),
// User AXIS interfaces
.usr_s_axis_rq_tready ( s_axis_rq_tready ),
.usr_s_axis_rq_tdata ( s_axis_rq_tdata ),
.usr_s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.usr_s_axis_rq_tuser ( s_axis_rq_tuser ),
.usr_s_axis_rq_tlast ( s_axis_rq_tlast ),
.usr_s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.usr_m_axis_rc_tdata ( m_axis_rc_tdata ),
.usr_m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.usr_m_axis_rc_tlast ( m_axis_rc_tlast ),
.usr_m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.usr_m_axis_rc_tuser ( m_axis_rc_tuser ),
.usr_m_axis_rc_tready ( m_axis_rc_tready )
// Rport CFG interface
// User CFG interface
// Rport PL interface
);
//--------------------------------------------------------------------------------------------------------------------//
endmodule // cgator_wrapper
这是cgator_wrapper的文件，ila核应该怎么配置？
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