[转]vivado管脚分配：PACKAGE_PIN or LOC

最新推荐文章于 2025-10-24 21:26:45 发布
转载 最新推荐文章于 2025-10-24 21:26:45 发布 · 5.7k 阅读 · 4 ·
CC 4.0 BY-SA版权
原文链接：http://www.cnblogs.com/tubujia/p/11169848.html

本文解释了在电子设计自动化(EDA)工具中，为何应当使用PACKAGE_PIN而非LOC属性来约束I/O端口的位置。尽管早期版本的Vivado等工具接受LOC属性，但未来版本可能仅支持PACKAGE_PIN。文章强调了PACKAGE_PIN属性的重要性，并说明了其与LOC属性的区别。

The correct one is PACKAGE_PIN. If you do a "report_property" on the port you will see that it has both a LOC and a PACKAGE_PIN property. The LOC constraint is the location on the die, as in IOB_XnnYmm - its grid coordinates. The PACKAGE_PIN property is the name of the package pin to which it is connected. So the correct one is the PACKAGE_PIN.

 

However, both in UCF as well as in the earliest versions of Vivado, the LOC property was used. So, when you apply a LOC property to a port, it actually cheats, and assigns the value to the PACKAGE_PIN property instead. As a result, the net result is exactly the same if you assign the LOC or PACKAGE_PIN property - but PACKAGE_PIN is the correct one, and in some future version of the tool it may no longer accept LOC in place of PACKAGE_PIN.

转载于:https://www.cnblogs.com/tubujia/p/11169848.html

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用户可能会混淆PACKAGE_PIN和LOC属性，需要指出在Vivado中PACKAGE_PIN是更现代的用法，替代了早期的LOC属性，但两者可能有相似的作用，取决于工具版本。 最后，总结使用场景和注意事项，确保用户能够正确应用该语句...
ERROR: set_pin_loc ddr_dq[0] AB17 in C:/Users/yangjiashuai/Desktop/imx415_hdmi_eth/uisrc/03_ip/alip/ph1a_ddr/ddr_ip.adc(5) is not a valid ADC command.
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根据错误信息，问题出现在约束文件（ddr_ip.adc）的第5行，使用了`set_pin_loc`命令试图将`ddr_dq[0]`分配到管脚AB17，但该命令不被识别为有效的ADC命令。 ADC命令通常指的是AMD/Xilinx设计约束（XDC）中的命令，但...
## Clock Signal set_property PACKAGE_PIN D4 [get_ports clk_in] set_property IOSTANDARD LVCMOS33 [get_ports clk_in] ## Reset Button (Active Low) set_property PACKAGE_PIN N12 [get_ports reset_p] set_property IOSTANDARD LVCMOS33 [get_ports reset_p] ## Control Buttons set_property PACKAGE_PIN K12 [get_ports start] set_property IOSTANDARD LVCMOS33 [get_ports start] set_property PACKAGE_PIN P13 [get_ports score_1] set_property IOSTANDARD LVCMOS33 [get_ports score_1] set_property PACKAGE_PIN L13 [get_ports change] set_property IOSTANDARD LVCMOS33 [get_ports change] set_property PACKAGE_PIN P11 [get_ports load_p] set_property IOSTANDARD LVCMOS33 [get_ports load_p] set_property PACKAGE_PIN P10 [get_ports stop] set_property IOSTANDARD LVCMOS33 [get_ports stop] ## Mode Selection Inputs (3-bit mode select: e.g., SW0, SW1, SW2) set_property PACKAGE_PIN P11 [get_ports {mode[0]}] set_property PACKAGE_PIN N11 [get_ports {mode[1]}] set_property PACKAGE_PIN P10 [get_ports {mode[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {mode[*]}] ## Seven-Segment Display Outputs # Segment data (active high): A -> lednum_select[0], ..., DP -> lednum_select[7] set_property PACKAGE_PIN L3 [get_ports {lednum_select[0]}] set_property PACKAGE_PIN L4 [get_ports {lednum_select[1]}] set_property PACKAGE_PIN N3 [get_ports {lednum_select[2]}] set_property PACKAGE_PIN K2 [get_ports {lednum_select[3]}] set_property PACKAGE_PIN L2 [get_ports {lednum_select[4]}] set_property PACKAGE_PIN K3 [get_ports {lednum_select[5]}] set_property PACKAGE_PIN L5 [get_ports {lednum_select[6]}] set_property PACKAGE_PIN M4 [get_ports {lednum_select[7]}] # Digit Select (bit_select active low) set_property PACKAGE_PIN K1 [get_ports {bit_select[0]}] set_property PACKAGE_PIN K5 [get_ports {bit_select[1]}] set_property PACKAGE_PIN J5 [get_ports {bit_select[2]}] set_property PACKAGE_PIN J1 [get_ports {bit_select[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {bit_select[*]}] set_property IOSTANDARD LVCMOS33 [get_ports {lednum_select[*]}] ## LED Alarm Output set_property PACKAGE_PIN G4 [get_ports LED] set_property IOSTANDARD LVCMOS33 [get_ports LED] set_property PACKAGE_PIN J5 [get_ports {bit_select[2]}] set_property PACKAGE_PIN J1 [get_ports {bit_select[3]}] set_property PACKAGE_PIN P11 [get_ports load_p] set_property PACKAGE_PIN P10 [get_ports stop] set_property PACKAGE_PIN R11 [get_ports load_p] set_property PACKAGE_PIN M12 [get_ports stop] 改正
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> `[Vivado 12-1411] Cannot set LOC property of ports...pad is already occupied` 这是因为同一个 FPGA 引脚被多个信号（端口）尝试占用。以下是根据你的约束内容进行的 **全面分析与修正**。 --- ### ❌ 存在...
`timescale 1ns / 1ps module Calculator( input clk, // 系统时钟 (100MHz) input rst, // 复位按钮 (S1) input [7:0] sw, // 拨码开关 SW0-SW7 input btn1, // 按钮S2 (运算类型选择) input btn2, // 按钮S3 (执行计算) output reg [7:0] led, // LED0-LED7 output [7:0] seg_en, // 数码管位选 output [7:0] seg_out // 数码管段选 ); // 系统参数定义 parameter IDLE = 2'b00; parameter INPUT_A = 2'b01; parameter INPUT_B = 2'b10; parameter DISPLAY_RESULT = 2'b11; // 运算类型定义 parameter ADD = 2'b00; parameter SUB = 2'b01; parameter MUL = 2'b10; // 状态寄存器 reg [1:0] state = IDLE; reg [1:0] next_state = IDLE; // 输入寄存器 reg [7:0] input_a = 0; reg [7:0] input_b = 0; reg [1:0] operation = ADD; // 计算结果 reg [15:0] result = 0; // 按钮消抖 - 改进版本 reg [19:0] btn1_debounce = 0; reg [19:0] btn2_debounce = 0; reg btn1_reg = 0; reg btn2_reg = 0; wire btn1_pressed; wire btn2_pressed; // 数码管显示控制 reg [31:0] display_value = 0; // 改进的按钮消抖逻辑 (边沿检测) always @(posedge clk) begin if (rst) begin btn1_reg <= 0; btn2_reg <= 0; btn1_debounce <= 0; btn2_debounce <= 0; end else begin // 按钮1消抖 btn1_reg <= btn1; if (btn1_reg != btn1) begin // 检测变化 btn1_debounce <= 0; end else if (btn1_debounce < 20'd200_000) begin // 2ms消抖 (100MHz时钟) btn1_debounce <= btn1_debounce + 1; end // 按钮2消抖 btn2_reg <= btn2; if (btn2_reg != btn2) begin btn2_debounce <= 0; end else if (btn2_debounce < 20'd200_000) begin btn2_debounce <= btn2_debounce + 1; end end end // 生成单周期脉冲信号 assign btn1_pressed = (btn1_debounce == 20'd200_000) && btn1; assign btn2_pressed = (btn2_debounce == 20'd200_000) && btn2; // 状态机 always @(posedge clk) begin if (rst) begin state <= IDLE; input_a <= 0; input_b <= 0; operation <= ADD; result <= 0; next_state <= IDLE; end else begin state <= next_state; case (state) IDLE: begin if (btn2_pressed) begin input_a <= get_input_value(sw); next_state <= INPUT_A; end else begin next_state <= IDLE; end end INPUT_A: begin if (btn1_pressed) begin // 循环切换运算类型 operation <= (operation == MUL) ? ADD : operation + 1; end if (btn2_pressed) begin input_b <= get_input_value(sw); next_state <= INPUT_B; end else begin next_state <= INPUT_A; end end INPUT_B: begin if (btn1_pressed) begin operation <= (operation == MUL) ? ADD : operation + 1; end if (btn2_pressed) begin // 执行计算 case (operation) ADD: result <= input_a + input_b; SUB: result <= input_a - input_b; MUL: result <= input_a * input_b; default: result <= input_a + input_b; endcase next_state <= DISPLAY_RESULT; end else begin next_state <= INPUT_B; end end DISPLAY_RESULT: begin if (btn2_pressed) begin // 返回输入状态 input_a <= result[7:0]; next_state <= INPUT_A; end else begin next_state <= DISPLAY_RESULT; end end default: next_state <= IDLE; endcase end end // 获取输入值 (0-9) function [7:0] get_input_value; input [7:0] sw; begin if (sw[5]) begin // SW5按下，使用5-9范围 get_input_value = 5 + sw[3:0]; end else begin // SW5未按下，使用0-4范围 get_input_value = sw[3:0]; end end endfunction // LED显示控制 always @(posedge clk) begin if (rst) begin led <= 0; end else if (state == DISPLAY_RESULT && result <= 255) begin led <= result[7:0]; end else begin led <= 0; end end // 数码管显示控制 always @(posedge clk) begin if (rst) begin display_value <= 32'h0000_0000; end else begin case (state) IDLE: display_value <= 32'h0000_0000; INPUT_A: display_value <= {24'h000000, input_a}; INPUT_B: display_value <= {16'h0000, input_a, input_b}; DISPLAY_RESULT: display_value <= result; default: display_value <= 32'h0000_0000; endcase end end // 数码管驱动实例化 Seg7Display seg7_display ( .clk(clk), .rst(rst), .data(display_value), .seg_en(seg_en), .seg_out(seg_out) ); endmodule // 数码管显示驱动模块 module Seg7Display( input clk, input rst, input [31:0] data, // 32位显示数据 output reg [7:0] seg_en, // 数码管位选 output reg [7:0] seg_out // 数码管段选 ); // 数码管扫描计数器 reg [19:0] scan_cnt = 0; reg [2:0] digit_sel = 0; // 数码管段码表 function [7:0] seg_table; input [3:0] digit; case (digit) 4'h0: seg_table = 8'b1100_0000; // 0 4'h1: seg_table = 8'b1111_1001; // 1 4'h2: seg_table = 8'b1010_0100; // 2 4'h3: seg_table = 8'b1011_0000; // 3 4'h4: seg_table = 8'b1001_1001; // 4 4'h5: seg_table = 8'b1001_0010; // 5 4'h6: seg_table = 8'b1000_0010; // 6 4'h7: seg_table = 8'b1111_1000; // 7 4'h8: seg_table = 8'b1000_0000; // 8 4'h9: seg_table = 8'b1001_0000; // 9 4'hA: seg_table = 8'b1000_1000; // A 4'hB: seg_table = 8'b1000_0011; // B 4'hC: seg_table = 8'b1100_0110; // C 4'hD: seg_table = 8'b1010_0001; // D 4'hE: seg_table = 8'b1000_0110; // E 4'hF: seg_table = 8'b1000_1110; // F default: seg_table = 8'b1111_1111; // 全灭 endcase endfunction // 当前显示的数字 reg [3:0] current_digit; // 扫描计数器 (1ms扫描周期) always @(posedge clk) begin if (rst) begin scan_cnt <= 0; digit_sel <= 0; end else begin if (scan_cnt == 20'd100_000) begin // 100MHz时钟，1ms = 100,000周期 scan_cnt <= 0; digit_sel <= (digit_sel == 3'd7) ? 3'd0 : digit_sel + 1; end else begin scan_cnt <= scan_cnt + 1; end end end // 数码管位选和段选 always @(posedge clk) begin if (rst) begin seg_en <= 8'b1111_1111; // 所有数码管关闭 seg_out <= 8'b1111_1111; // 段选全灭 end else begin // 位选信号 seg_en <= ~(8'b0000_0001 << digit_sel); // 根据当前选择的数码管位，提取对应数据 case (digit_sel) 0: current_digit = data[3:0]; 1: current_digit = data[7:4]; 2: current_digit = data[11:8]; 3: current_digit = data[15:12]; 4: current_digit = data[19:16]; 5: current_digit = data[23:20]; 6: current_digit = data[27:24]; 7: current_digit = data[31:28]; default: current_digit = 4'hF; endcase // 段选信号 seg_out <= seg_table(current_digit); end end endmodule和# 时钟约束 create_clock -period 10.000 -name clk [get_ports clk] # 复位按钮 set_property PACKAGE_PIN L18 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports rst] # 功能按钮 set_property PACKAGE_PIN C9 [get_ports btn1] set_property IOSTANDARD LVCMOS33 [get_ports btn1] set_property PACKAGE_PIN B5 [get_ports btn2] set_property IOSTANDARD LVCMOS33 [get_ports btn2] # 拨码开关 set_property PACKAGE_PIN AB6 [get_ports {sw[0]}] set_property PACKAGE_PIN Y4 [get_ports {sw[1]}] set_property PACKAGE_PIN AA4 [get_ports {sw[2]}] set_property PACKAGE_PIN R6 [get_ports {sw[3]}] set_property PACKAGE_PIN T6 [get_ports {sw[4]}] set_property PACKAGE_PIN T4 [get_ports {sw[5]}] set_property PACKAGE_PIN U4 [get_ports {sw[6]}] set_property PACKAGE_PIN V5 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports sw*] # LED灯 set_property PACKAGE_PIN V4 [get_ports {led[0]}] set_property PACKAGE_PIN U6 [get_ports {led[1]}] set_property PACKAGE_PIN U5 [get_ports {led[2]}] set_property PACKAGE_PIN V7 [get_ports {led[3]}] set_property PACKAGE_PIN W7 [get_ports {led[4]}] set_property PACKAGE_PIN W6 [get_ports {led[5]}] set_property PACKAGE_PIN W5 [get_ports {led[6]}] set_property PACKAGE_PIN U7 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports led*] # 数码管段选 set_property PACKAGE_PIN R21 [get_ports {seg_out[0]}] set_property PACKAGE_PIN P20 [get_ports {seg_out[1]}] set_property PACKAGE_PIN P21 [get_ports {seg_out[2]}] set_property PACKAGE_PIN N15 [get_ports {seg_out[3]}] set_property PACKAGE_PIN P15 [get_ports {seg_out[4]}] set_property PACKAGE_PIN P17 [get_ports {seg_out[5]}] set_property PACKAGE_PIN P18 [get_ports {seg_out[6]}] set_property PACKAGE_PIN T16 [get_ports {seg_out[7]}] set_property IOSTANDARD LVCMOS33 [get_ports seg_out*] # 数码管位选 set_property PACKAGE_PIN M20 [get_ports {seg_en[0]}] set_property PACKAGE_PIN N19 [get_ports {seg_en[1]}] set_property PACKAGE_PIN N20 [get_ports {seg_en[2]}] set_property PACKAGE_PIN M21 [get_ports {seg_en[3]}] set_property PACKAGE_PIN M22 [get_ports {seg_en[4]}] set_property PACKAGE_PIN N22 [get_ports {seg_en[5]}] set_property PACKAGE_PIN P22 [get_ports {seg_en[6]}] set_property PACKAGE_PIN R20 [get_ports {seg_en[7]}] set_property IOSTANDARD LVCMOS33 [get_ports seg_en*] # 系统时钟 set_property PACKAGE_PIN M19 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk]这是所有的代码文件，在产生比特流时发生上述报错，是啥意思以及如何修改
10-09
查看输出文件中 `btn1` 和 `btn2` 是否有对应的 `Package Pin`。如果没有，则约束未生效。 #### ✅ 步骤 4：强制更新约束并重新运行 在 Tcl 控制台依次执行： ```tcl reset_run impl_1 reset_run synth_1 launch_...
[Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 33 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: key12, and key13. [Common 17-69] Command failed: Specified output directory "./output" does not exist. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 33 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: key12, and key13. 所以到底该怎么改 ## =================================== ## 时钟输入（Bank 35） ## =================================== set_property PACKAGE_PIN M19 [get_ports clk_100m] set_property IOSTANDARD LVCMOS33 [get_ports clk_100m] create_clock -period 10.000 [get_ports clk_100m] set_property IOSTANDARD LVCMOS33 [get_iobanks 35] ## =================================== ## 用户接口信号（Bank 34） ## =================================== set_property PACKAGE_PIN L18 [get_ports rst_btn] set_property IOSTANDARD LVCMOS33 [get_ports rst_btn] set_property PACKAGE_PIN W19 [get_ports key12] set_property IOSTANDARD LVCMOS33 [get_ports key12] set_property PACKAGE_PIN U18 [get_ports key13] set_property IOSTANDARD LVCMOS33 [get_ports key13] # 所有开关、LED、数码管均位于 Bank 34 set_property PACKAGE_PIN AB6 [get_ports {sw[0]}] set_property PACKAGE_PIN Y4 [get_ports {sw[1]}] set_property PACKAGE_PIN AA4 [get_ports {sw[2]}] set_property PACKAGE_PIN R6 [get_ports {sw[3]}] set_property PACKAGE_PIN T6 [get_ports {sw[4]}] set_property PACKAGE_PIN T4 [get_ports {sw[5]}] set_property PACKAGE_PIN U4 [get_ports {sw[6]}] set_property PACKAGE_PIN V5 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports sw[*]] set_property PACKAGE_PIN V4 [get_ports {led[0]}] set_property PACKAGE_PIN U6 [get_ports {led[1]}] set_property PACKAGE_PIN U5 [get_ports {led[2]}] set_property PACKAGE_PIN V7 [get_ports {led[3]}] set_property PACKAGE_PIN W7 [get_ports {led[4]}] set_property PACKAGE_PIN W6 [get_ports {led[5]}] set_property PACKAGE_PIN W5 [get_ports {led[6]}] set_property PACKAGE_PIN U7 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports led[*]] # 数码管段选与位选 set_property PACKAGE_PIN R21 [get_ports {seg_led[7]}] set_property PACKAGE_PIN P20 [get_ports {seg_led[6]}] set_property PACKAGE_PIN P21 [get_ports {seg_led[5]}] set_property PACKAGE_PIN N15 [get_ports {seg_led[4]}] set_property PACKAGE_PIN P15 [get_ports {seg_led[3]}] set_property PACKAGE_PIN P17 [get_ports {seg_led[2]}] set_property PACKAGE_PIN P18 [get_ports {seg_led[1]}] set_property PACKAGE_PIN T16 [get_ports {seg_led[0]}] set_property PACKAGE_PIN M20 [get_ports {seg_sel[0]}] set_property PACKAGE_PIN N19 [get_ports {seg_sel[1]}] set_property PACKAGE_PIN N20 [get_ports {seg_sel[2]}] set_property PACKAGE_PIN M21 [get_ports {seg_sel[3]}] set_property PACKAGE_PIN M22 [get_ports {seg_sel[4]}] set_property PACKAGE_PIN N22 [get_ports {seg_sel[5]}] set_property PACKAGE_PIN P22 [get_ports {seg_sel[6]}] set_property PACKAGE_PIN R20 [get_ports {seg_sel[7]}] set_property IOSTANDARD LVCMOS33 [get_ports seg_led[*]] set_property IOSTANDARD LVCMOS33 [get_ports seg_sel[*]] # 统一设置 Bank 34 set_property IOSTANDARD LVCMOS33 [get_iobanks 34]
10-10
set_property PACKAGE_PIN M19 [get_ports clk_100m] set_property IOSTANDARD LVCMOS33 [get_ports clk_100m] create_clock -period 10.000 [get_ports clk_100m] ## =================================== ## 用户...
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