SDRAM 布线说明

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DDR2 SDRAM信号易受噪声、时钟偏斜和抖动影响，从而影响信号与时钟的时间裕度和最大吞吐量。SDRAM器件应放置在处理器附近，配备充足的布线通道，使信号轨迹在处理器和SDRAM封装之间。信号轨迹应控制为50欧姆单端阻抗，并在相邻层上有稳定的参考平面。差分对如clk/clkn和dqs/dqsn应以100欧姆差分阻抗运行。当使用两个或多个SDRAM封装连接到相同的DDR2 SDRAM总线时，信号应以T形架构路由，T形短腿长度相同以减少反射效应。应注意避免在DDR2 SDRAM信号路由区域布置其他高速信号，以免发生串扰。

摘抄于：http://processors.wiki.ti.com/index.php/Sitara_Layout_Checklist#DDR2_SDRAM_Signals

DDR2 SDRAM Signals

DDR2 SDRAM signals are particularly prone to noise, skew, and jitter which will all affect the timing margins of the signals with respect to the clock and consequently the overall max throughput that can be achieved. The SDRAM devices should be placed close to the processor with adequate routing channels to place the signal traces in between the processor and the SDRAM packages. The traces should be controlled to 50ohm signal ended impedance for the length of the traces with solid reference planes on the adjacent layer. The differential pairs such as clk/clkn and dqs/dqsn should be run with controlled impedance of differential 100ohms.

When two or more SDRAM packages are used to connect to the same DDR2 SDRAM bus, then the signals which run to both packages should be routed in a T architecture with the short legs of the T to each SDRAM package having the same length to minimize the reflection effects. Be careful not to run other high speed signals from other non-SDRAM busses across the area where the DDR2 SDRAM signals are routed as crosstalk from these aggressor nets can affect the signal characteristics of the DDR2 SDRAM signals. All the SDRAM signals should be length matched to the clk/clkn signal pair length average. The clk/clkn signals should be length matched to each other to within 10mils.