SDRAM 布线说明

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于 2018-01-07 20:35:17 发布

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分类专栏： hardware

本文链接：https://blog.youkuaiyun.com/daniel117/article/details/78997210

DDR2 SDRAM信号易受噪声、时钟偏斜和抖动影响，从而影响信号与时钟的时间裕度和最大吞吐量。SDRAM器件应放置在处理器附近，配备充足的布线通道，使信号轨迹在处理器和SDRAM封装之间。信号轨迹应控制为50欧姆单端阻抗，并在相邻层上有稳定的参考平面。差分对如clk/clkn和dqs/dqsn应以100欧姆差分阻抗运行。当使用两个或多个SDRAM封装连接到相同的DDR2 SDRAM总线时，信号应以T形架构路由，T形短腿长度相同以减少反射效应。应注意避免在DDR2 SDRAM信号路由区域布置其他高速信号，以免发生串扰。

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摘抄于：http://processors.wiki.ti.com/index.php/Sitara_Layout_Checklist#DDR2_SDRAM_Signals

DDR2 SDRAM Signals

DDR2 SDRAM signals are particularly prone to noise, skew, and jitter which will all affect the timing margins of the signals with respect to the clock and consequently the overall max throughput that can be achieved. The SDRAM devices should be placed close to the processor with adequate routing channels to place the signal traces in between the processor and the SDRAM packages. The traces should be controlled to 50ohm signal ended impedanc