VHDL中的warning集锦

最新推荐文章于 2020-03-10 15:18:36 发布

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本文解决Xilinx ISE中使用IP核时出现的“Instantiating blackbox module”警告问题，介绍如何通过修改HDL代码避免该警告，并提供VHDL和Verilog示例。

1、Instantiating black box module warning<摘录>

用Xilinx ISE综合使用了IP核的设计，弹出警告错误

AR #29792 - XST - "WARNING:Xst:2211 - "file_name" line #: Instantiating black box module <module_name>"

该警告可无视，如想消除，见下

Description

Keywords: VHDL, EDIF, EDF, EDN, NGO, NGC

When a "black box" is instantiated, the following warning occurs:

"WARNING: Xst:766 - file_name (Line #). Generating a Black Box for component <component_name>."

Solution

A black box is any instantiated component that is not represented by HDL code, but rather by another netlist format. Synthesis tools will generally report some kind of warning when a black box (an instantiated component with no associated VHDL code) is detected.

Examples of black boxes include:
- CORE Generator modules
- Instantiated EDIF files
- Instantiated primitives

If you are instantiating a component that is represented by something other than HDL code, no response to the warning message is needed. If your intent was not to instantiate a black box, check your component declaration and instantiation to ensure that the component is properly represented by HDL code.

To avoid "black box" warning messages, add the following lines to your HDL code:

VHDL:

architecture <architecture_name>
:
attribute box_type : string;
attribute box_type of <component_name> : component is "black_box";
:
begin

Verilog:
//synthesis attribute box_type <module_name> "black_box"