Seq_file File System实例剖析

本文介绍Linux内核中的Seq_file机制,这是一种改进的proc文件系统接口,用于高效地读取内核数据。Seq_file通过定义一系列操作函数如start(), next(), show(), stop()来遍历和展示数据,适用于链表、数组等数据结构。

Seq_file File System
针对proc文件的不足而诞生了Seq_file。
Seq_file的实现基于proc文件。使用Seq_file,用户必须抽象出一个链接对象,然后可以依次遍历这个链接对象。这个链接对象可以是链表,数组,哈希表等等。
编程接口
Seq_file必须实现四个操作函数:start(), next(), show(), stop()

struct seq_operations {
    void * (*start) (struct seq_file *m, loff_t *pos);
    void (*stop) (struct seq_file *m, void *v);
    void * (*next) (struct seq_file *m, void *v, loff_t *pos);
    int (*show) (struct seq_file *m, void *v);
};

start()
主要实现初始化工作,在遍历一个链接对象开始时,调用。返回一个链接对象的偏移或者SEQ_START_TOKEN(表征这是所有循环的开始)。出错返回ERR_PTR。
stop():
当所有链接对象遍历结束时调用。主要完成一些清理工作。
next():
用来在遍历中寻找下一个链接对象。返回下一个链接对象或者NULL(遍历结束)。
show():
对遍历对象进行操作的函数。主要是调用seq_printf(), seq_puts()之类的函数,打印出这个对象节点的信息。
下图描述了seq_file函数对一个链表的遍历。

2、重要的数据结构
除了struct seq_operations以外,另一个最重要的数据结构是struct seq_file:
struct seq_file {
        char *buf;
        size_t size;
        size_t from;
        size_t count;
        loff_t index;
        u64 version;
        struct mutex lock;
        const struct seq_operations *op;
        void *private;
};
该结构会在seq_open函数调用中分配,然后作为参数传递给每个seq_file的操作函数。Privat变量可以用来在各个操作函数之间传递参数。

seq_hello.c
#include <net/net_namespace.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>

#define PROC_NAME "test_proc"
#define MAX_LINES 10

typedef struct item
{
    unsigned long key;
    unsigned char value;
}user_item;

user_item items[4];

MODULE_AUTHOR("ZHANG JIE:iptabler@mail.com");
MODULE_LICENSE("GPL");

static void *my_seq_start(struct seq_file *s, loff_t *pos)
{
        static unsigned long counter = 0;
        printk(KERN_INFO"Invoke start/n");

        if ( *pos == 0 )
        {
                /* yes => return a non null value to begin the sequence */
                return &counter;
        }
        else
        {
                /* no => it's the end of the sequence, return end to stop reading */
                *pos = 0;
                return NULL;
        }
}

static void *my_seq_next(struct seq_file *s, void *v, loff_t *pos)
{
    unsigned long *tmp_v = (unsigned long *)v;
     if (*pos < MAX_LINES) {
        (*tmp_v)++;
        (*pos)++;
        return tmp_v;
        }
    else
    {
        *pos = 0;
        return NULL;
    }
}

static void my_seq_stop(struct seq_file *s, void *v)
{
    printk("Invoke stop/n");
}

static int my_seq_show(struct seq_file *s, void *v)
{
       int i;
        loff_t *spos = (loff_t *) v;
    for (i = 0; i < 4; i++)
    {
     items[i].key = *spos;
    }
      items[0].value = '0';
      items[1].value = '1';
      items[2].value = '2';
      items[3].value = '3';
      seq_printf(s, "%ld=%c,%ld=%c,%ld=%c,%ld=%c;/n", items[0].key,
         items[0].value, items[1].key, items[1].value, items[2].key,
         items[2].value, items[3].key, items[3].value);
        return 0;
}

static struct seq_operations my_seq_ops = {
        .start = my_seq_start,
        .next = my_seq_next,
        .stop = my_seq_stop,
        .show = my_seq_show
};

static int my_open(struct inode *inode, struct file *file)
{
        return seq_open(file, &my_seq_ops);
};

static struct file_operations my_file_ops = {
        .owner = THIS_MODULE,
        .open = my_open,
        .read = seq_read,
        .llseek = seq_lseek,
        .release = seq_release
};

int init_module(void)
{
        struct proc_dir_entry *entry;
        entry = create_proc_entry(PROC_NAME, 0, init_net.proc_net);
        if (entry) {
                entry->proc_fops = &my_file_ops;
        }
        printk(KERN_INFO"Initialze /proc/net/test_proc success!/n");
        return 0;
}

void cleanup_module(void)
{
        remove_proc_entry(PROC_NAME, init_net.proc_net);
        printk(KERN_INFO"Remove /proc/net/test_proc success!/n");
}

Makefile
obj-m := seq_hello.o
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)

default:
    $(MAKE) -C $(KDIR) M=$(PWD) modules
clean:
    $(RM) *.o *.mod.c *.ko *.symvers *.markers *.order

[root@zj:~/Desktop/net/seq]# cat /proc/net/test_proc
0=0,0=1,0=2,0=3;
1=0,1=1,1=2,1=3;
2=0,2=1,2=2,2=3;
3=0,3=1,3=2,3=3;
4=0,4=1,4=2,4=3;
5=0,5=1,5=2,5=3;
6=0,6=1,6=2,6=3;
7=0,7=1,7=2,7=3;
8=0,8=1,8=2,8=3;
9=0,9=1,9=2,9=3;
10=0,10=1,10=2,10=3;

public static void main(String[] args) { Trace.traceBegin(Trace.TRACE_TAG_ACTIVITY_MANAGER, "ActivityThreadMain"); final long startTime = SystemClock.uptimeMillis(); // Install selective syscall interception AndroidOs.install(); // CloseGuard defaults to true and can be quite spammy. We // disable it here, but selectively enable it later (via // StrictMode) on debug builds, but using DropBox, not logs. CloseGuard.setEnabled(false); Environment.initForCurrentUser(); // Make sure TrustedCertificateStore looks in the right place for CA certificates final File configDir = Environment.getUserConfigDirectory(UserHandle.myUserId()); TrustedCertificateStore.setDefaultUserDirectory(configDir); // Call per-process mainline module initialization. initializeMainlineModules(); Process.setArgV0("<pre-initialized>"); Looper.prepareMainLooper(); // Find the value for {@link #PROC_START_SEQ_IDENT} if provided on the command line. // It will be in the format "seq=114" long startSeq = 0; if (args != null) { for (int i = args.length - 1; i >= 0; --i) { if (args[i] != null && args[i].startsWith(PROC_START_SEQ_IDENT)) { startSeq = Long.parseLong( args[i].substring(PROC_START_SEQ_IDENT.length())); } } } ActivityThread thread = new ActivityThread(); thread.attach(false, startSeq); if (sMainThreadHandler == null) { sMainThreadHandler = thread.getHandler(); } if (false) { Looper.myLooper().setMessageLogging(new LogPrinter(Log.DEBUG, "ActivityThread")); } //#ifdef OPLUS_EXTENSION_HOOK //Jie.Zhang@ANDROID.PERFORMANCE, 2021/12/14, Add for quality information update ExtLoader.type(IOplusJankMonitorExt.class).create().setLaunchStageTime("activityThreadMain", "activityThreadMain", startTime); //#endif /* OPLUS_EXTENSION_HOOK */ // End of event ActivityThreadMain. Trace.traceEnd(Trace.TRACE_TAG_ACTIVITY_MANAGER); //#ifdef MTK_ONLY_FEATURE_ANR_DEBUG STATIC_EXT.setMessageLogger(); //#endif /*MTK_ONLY_FEATURE_ANR_DEBUG*/ // #ifdef OPLUS_BUG_DEBUG // collins@ANDROID.STABILTIY, 2022/10/20, add bitmap tracker feature thread.mOplusActivityThreadExt.enableBitmapTracking(); // #endif /* OPLUS_BUG_DEBUG */ Looper.loop(); throw new RuntimeException("Main thread loop unexpectedly exited"); }
11-08
//----------------------------------------------------------------------------- // // (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // // Project : UltraScale+ FPGA PCI Express v4.0 Integrated Block // File : cgator_wrapper.v // Version : 1.3 //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // // Project : Ultrascale FPGA Gen4 Integrated Block for PCI Express // File : cgator_wrapper.v // Version : 1.0 //----------------------------------------------------------------------------- `timescale 1ns/1ns (* DowngradeIPIdentifiedWarnings = "yes" *) module cgator_wrapper #( // Configurator parameters parameter PCIE_LOCATION = "X0Y0", parameter TCQ = 1, parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "TRUE", parameter PIPE_SIM_MODE = "FALSE", parameter EXTRA_PIPELINE = 1, parameter ROM_FILE = "cgator_cfg_rom.data", parameter ROM_SIZE = 32, parameter [15:0] REQUESTER_ID = 16'h10EE, parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking Module parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4, // 1- GEN1, 2 - GEN2, 4 - GEN3 parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h8, // 1- X1, 2 - X2, 4 - X4, 8 - X8 parameter PL_DISABLE_EI_INFER_IN_L0 = "TRUE", parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE", // USER_CLK[1/2]_FREQ :[0] = Disable user clock; [1] = 31.25 MHz; [2] = 62.50 MHz (default); [3] = 125.00 MHz; [4] = 250.00 MHz; [5] = 500.00 MHz; parameter integer USER_CLK2_FREQ = 2, parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz parameter AXISTEN_IF_RQ_PARITY_CHECK = "FALSE", parameter AXI4_CQ_TUSER_WIDTH = 88, parameter AXI4_CC_TUSER_WIDTH = 33, parameter AXI4_RQ_TUSER_WIDTH = 62, parameter AXI4_RC_TUSER_WIDTH = 75, parameter C_DATA_WIDTH = 64, parameter KEEP_WIDTH = C_DATA_WIDTH / 32 ) ( //------------------------------------------------------- // 0. Configurator I/Os //------------------------------------------------------- input start_config, output finished_config, output failed_config, //------------------------------------------------------- // 1. PCI Express (pci_exp) Interface //------------------------------------------------------- output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_txp, output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_txn, input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_rxp, input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_rxn, //------------------------------------------------------- // 2. Transaction (AXIS) Interface //------------------------------------------------------- output user_clk_out, output user_reset_out, output user_lnk_up, output phy_rdy_out, //------------------------------------------------------- output s_axis_rq_tready, input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, input [AXI4_RQ_TUSER_WIDTH-1:0] s_axis_rq_tuser, input s_axis_rq_tlast, input s_axis_rq_tvalid, //------------------------------------------------------- output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, output m_axis_rc_tlast, output m_axis_rc_tvalid, output [AXI4_RC_TUSER_WIDTH-1:0] m_axis_rc_tuser, input m_axis_rc_tready, //------------------------------------------------------- output wire [C_DATA_WIDTH-1:0] m_axis_cq_tdata, output wire [AXI4_CQ_TUSER_WIDTH-1:0] m_axis_cq_tuser, output wire m_axis_cq_tlast, output wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep, output wire m_axis_cq_tvalid, input m_axis_cq_tready, //------------------------------------------------------- input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, input [AXI4_CC_TUSER_WIDTH-1:0] s_axis_cc_tuser, input s_axis_cc_tlast, input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, input s_axis_cc_tvalid, output wire [3:0] s_axis_cc_tready, //------------------------------------------------------- // 3. Configuration (CFG) Interface - EP and RP //------------------------------------------------------- output [3:0] pcie_tfc_nph_av, output [3:0] pcie_tfc_npd_av, //------------------------------------------------------- // Error Reporting Interface //------------------------------------------------------- output wire [5:0] pcie_rq_seq_num0, output wire pcie_rq_seq_num_vld0, output wire [5:0] pcie_rq_seq_num1, output wire pcie_rq_seq_num_vld1, output wire [7:0] pcie_rq_tag0, output wire pcie_rq_tag_vld0, output wire [7:0] pcie_rq_tag1, output wire pcie_rq_tag_vld1, output wire [3:0] pcie_rq_tag_av, input [1:0] pcie_cq_np_req, output [5:0] pcie_cq_np_req_count, output cfg_phy_link_down, output [1:0] cfg_phy_link_status, output [2:0] cfg_negotiated_width, output [1:0] cfg_current_speed, output [1:0] cfg_max_payload, output [2:0] cfg_max_read_req, output [15:0] cfg_function_status, output [11:0] cfg_function_power_state, output [503:0] cfg_vf_status, output [755:0] cfg_vf_power_state, output [1:0] cfg_link_power_state, output cfg_err_cor_out, output cfg_err_nonfatal_out, output cfg_err_fatal_out, output [4:0] cfg_local_error_out, output cfg_local_error_valid, output [5:0] cfg_ltssm_state, output [1:0] cfg_rx_pm_state, output [1:0] cfg_tx_pm_state, output [3:0] cfg_rcb_status, output [1:0] cfg_obff_enable, output cfg_pl_status_change, output [3:0] cfg_tph_requester_enable, output [11:0] cfg_tph_st_mode, output [251:0] cfg_vf_tph_requester_enable, output [755:0] cfg_vf_tph_st_mode, //------------------------------------------------------- // Interrupt Interface Signals //------------------------------------------------------- input [3:0] cfg_interrupt_int, input [1:0] cfg_interrupt_pending, output cfg_interrupt_sent, output [3:0] cfg_interrupt_msi_enable, output [11:0] cfg_interrupt_msi_mmenable, output cfg_interrupt_msi_mask_update, output [31:0] cfg_interrupt_msi_data, input [1:0] cfg_interrupt_msi_select, input [31:0] cfg_interrupt_msi_int, input [63:0] cfg_interrupt_msi_pending_status, output cfg_interrupt_msi_sent, output cfg_interrupt_msi_fail, input [2:0] cfg_interrupt_msi_attr, input cfg_interrupt_msi_tph_present, input [1:0] cfg_interrupt_msi_tph_type, input [7:0] cfg_interrupt_msi_tph_st_tag, input cfg_interrupt_msi_pending_status_data_enable, input [3:0] cfg_interrupt_msi_pending_status_function_num, input [2:0] cfg_interrupt_msi_function_number, //------------------------------------------------------- input sys_clk, input sys_clk_gt, input sys_reset_n //------------------------------------------------------- ); //--------------------------------------------------------------------------------------------------------------------// // Connections between Root Port and Configurator //--------------------------------------------------------------------------------------------------------------------// wire [3:0] rport_s_axis_rq_tready; wire [C_DATA_WIDTH-1:0] rport_s_axis_rq_tdata; wire [KEEP_WIDTH-1:0] rport_s_axis_rq_tkeep; wire [AXI4_RQ_TUSER_WIDTH-1:0] rport_s_axis_rq_tuser; wire rport_s_axis_rq_tlast; wire rport_s_axis_rq_tvalid; wire [C_DATA_WIDTH-1:0] rport_m_axis_rc_tdata; wire [KEEP_WIDTH-1:0] rport_m_axis_rc_tkeep; wire rport_m_axis_rc_tlast; wire rport_m_axis_rc_tvalid; wire rport_m_axis_rc_tready; wire [AXI4_RC_TUSER_WIDTH-1:0] rport_m_axis_rc_tuser; // wire cfg_msg_received; // wire [7 : 0] cfg_msg_received_data; // wire [4 : 0] cfg_msg_received_type; // ila_32 ila_cgator_0 ( // .clk(user_clk_out), // .probe0({ // cfg_msg_received, // cfg_msg_received_data, // cfg_msg_received_type // }) // ); //---------------------------------------------------------------------------------------// // Core Top Level Wrapper generate if (PCIE_LOCATION == "X0Y0") begin pcie4_uscale_plus_0 pcie4_uscale_plus_0_i ( //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// // Tx .pci_exp_txn ( pci_exp_txn ), .pci_exp_txp ( pci_exp_txp ), // Rx .pci_exp_rxn ( pci_exp_rxn ), .pci_exp_rxp ( pci_exp_rxp ), //---------------------------------------------------------------------------------------// // AXI Interface // //---------------------------------------------------------------------------------------// .user_clk ( user_clk_out ), .user_reset ( user_reset_out ), .user_lnk_up ( user_lnk_up ), .phy_rdy_out ( phy_rdy_out ), .s_axis_rq_tlast ( rport_s_axis_rq_tlast ), .s_axis_rq_tdata ( rport_s_axis_rq_tdata ), .s_axis_rq_tuser ( rport_s_axis_rq_tuser ), .s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ), .s_axis_rq_tready ( rport_s_axis_rq_tready ), .s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ), .m_axis_rc_tdata ( rport_m_axis_rc_tdata ), .m_axis_rc_tuser ( rport_m_axis_rc_tuser ), .m_axis_rc_tlast ( rport_m_axis_rc_tlast ), .m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ), .m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ), .m_axis_rc_tready ( rport_m_axis_rc_tready ), .m_axis_cq_tdata ( m_axis_cq_tdata ), .m_axis_cq_tuser ( m_axis_cq_tuser ), .m_axis_cq_tlast ( m_axis_cq_tlast ), .m_axis_cq_tkeep ( m_axis_cq_tkeep ), .m_axis_cq_tvalid ( m_axis_cq_tvalid ), .m_axis_cq_tready ( m_axis_cq_tready ), .s_axis_cc_tdata ( s_axis_cc_tdata ), .s_axis_cc_tuser ( s_axis_cc_tuser ), .s_axis_cc_tlast ( s_axis_cc_tlast ), .s_axis_cc_tkeep ( s_axis_cc_tkeep ), .s_axis_cc_tvalid ( s_axis_cc_tvalid ), .s_axis_cc_tready ( s_axis_cc_tready ), //---------------------------------------------------------------------------------------// // Configuration (CFG) Interface // //---------------------------------------------------------------------------------------// .pcie_tfc_nph_av ( pcie_tfc_nph_av ), .pcie_tfc_npd_av ( pcie_tfc_npd_av ), .pcie_rq_seq_num0 ( pcie_rq_seq_num0) , .pcie_rq_seq_num_vld0 ( pcie_rq_seq_num_vld0) , .pcie_rq_seq_num1 ( pcie_rq_seq_num1) , .pcie_rq_seq_num_vld1 ( pcie_rq_seq_num_vld1) , .pcie_rq_tag0 ( pcie_rq_tag0) , .pcie_rq_tag1 ( pcie_rq_tag1) , .pcie_rq_tag_av ( pcie_rq_tag_av) , .pcie_rq_tag_vld0 ( pcie_rq_tag_vld0) , .pcie_rq_tag_vld1 ( pcie_rq_tag_vld1) , .pcie_cq_np_req ( pcie_cq_np_req ), .pcie_cq_np_req_count ( pcie_cq_np_req_count ), .cfg_phy_link_down ( cfg_phy_link_down ), .cfg_phy_link_status ( cfg_phy_link_status), .cfg_negotiated_width ( cfg_negotiated_width ), .cfg_current_speed ( cfg_current_speed ), .cfg_max_payload ( cfg_max_payload ), .cfg_max_read_req ( cfg_max_read_req ), .cfg_function_status ( cfg_function_status ), .cfg_function_power_state ( cfg_function_power_state ), .cfg_vf_status ( cfg_vf_status ), .cfg_vf_power_state ( cfg_vf_power_state ), .cfg_link_power_state ( cfg_link_power_state ), // Error Reporting Interface .cfg_err_cor_out ( cfg_err_cor_out ), .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), .cfg_err_fatal_out ( cfg_err_fatal_out ), .cfg_local_error_out ( cfg_local_error_out ), .cfg_local_error_valid ( cfg_local_error_valid ), .cfg_ltssm_state ( cfg_ltssm_state ), .cfg_rx_pm_state ( cfg_rx_pm_state ), .cfg_tx_pm_state ( cfg_tx_pm_state ), .cfg_rcb_status ( cfg_rcb_status ), .cfg_obff_enable ( cfg_obff_enable ), .cfg_pl_status_change ( cfg_pl_status_change ), .cfg_tph_requester_enable ( cfg_tph_requester_enable ), .cfg_tph_st_mode ( cfg_tph_st_mode ), .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), // /* agan add @ 20220603, for debug*/ // .cfg_msg_received ( cfg_msg_received ) , // .cfg_msg_received_data ( cfg_msg_received_data ), // .cfg_msg_received_type ( cfg_msg_received_type ), // // //-------------------------------------------------------------------------------// // EP Only // //-------------------------------------------------------------------------------// // Interrupt Interface Signals .cfg_interrupt_int ( cfg_interrupt_int ), .cfg_interrupt_pending ( {2'b0,cfg_interrupt_pending} ), .cfg_interrupt_sent ( cfg_interrupt_sent ), .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status [31:0]), .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), .cfg_interrupt_msi_pending_status_function_num (2'b0), .cfg_interrupt_msi_pending_status_data_enable (1'b0), .cfg_interrupt_msi_function_number (8'b0 ), //--------------------------------------------------------------------------------------// // System(SYS) Interface // //--------------------------------------------------------------------------------------// .sys_clk ( sys_clk ), .sys_clk_gt ( sys_clk_gt ), .sys_reset ( sys_reset_n ) ); end else if (PCIE_LOCATION == "X0Y1") begin pcie4_uscale_plus_1 pcie4_uscale_plus_0_i ( //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// // Tx .pci_exp_txn ( pci_exp_txn ), .pci_exp_txp ( pci_exp_txp ), // Rx .pci_exp_rxn ( pci_exp_rxn ), .pci_exp_rxp ( pci_exp_rxp ), //---------------------------------------------------------------------------------------// // AXI Interface // //---------------------------------------------------------------------------------------// .user_clk ( user_clk_out ), .user_reset ( user_reset_out ), .user_lnk_up ( user_lnk_up ), .phy_rdy_out ( phy_rdy_out ), .s_axis_rq_tlast ( rport_s_axis_rq_tlast ), .s_axis_rq_tdata ( rport_s_axis_rq_tdata ), .s_axis_rq_tuser ( rport_s_axis_rq_tuser ), .s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ), .s_axis_rq_tready ( rport_s_axis_rq_tready ), .s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ), .m_axis_rc_tdata ( rport_m_axis_rc_tdata ), .m_axis_rc_tuser ( rport_m_axis_rc_tuser ), .m_axis_rc_tlast ( rport_m_axis_rc_tlast ), .m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ), .m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ), .m_axis_rc_tready ( rport_m_axis_rc_tready ), .m_axis_cq_tdata ( m_axis_cq_tdata ), .m_axis_cq_tuser ( m_axis_cq_tuser ), .m_axis_cq_tlast ( m_axis_cq_tlast ), .m_axis_cq_tkeep ( m_axis_cq_tkeep ), .m_axis_cq_tvalid ( m_axis_cq_tvalid ), .m_axis_cq_tready ( m_axis_cq_tready ), .s_axis_cc_tdata ( s_axis_cc_tdata ), .s_axis_cc_tuser ( s_axis_cc_tuser ), .s_axis_cc_tlast ( s_axis_cc_tlast ), .s_axis_cc_tkeep ( s_axis_cc_tkeep ), .s_axis_cc_tvalid ( s_axis_cc_tvalid ), .s_axis_cc_tready ( s_axis_cc_tready ), //---------------------------------------------------------------------------------------// // Configuration (CFG) Interface // //---------------------------------------------------------------------------------------// .pcie_tfc_nph_av ( pcie_tfc_nph_av ), .pcie_tfc_npd_av ( pcie_tfc_npd_av ), .pcie_rq_seq_num0 ( pcie_rq_seq_num0) , .pcie_rq_seq_num_vld0 ( pcie_rq_seq_num_vld0) , .pcie_rq_seq_num1 ( pcie_rq_seq_num1) , .pcie_rq_seq_num_vld1 ( pcie_rq_seq_num_vld1) , .pcie_rq_tag0 ( pcie_rq_tag0) , .pcie_rq_tag1 ( pcie_rq_tag1) , .pcie_rq_tag_av ( pcie_rq_tag_av) , .pcie_rq_tag_vld0 ( pcie_rq_tag_vld0) , .pcie_rq_tag_vld1 ( pcie_rq_tag_vld1) , .pcie_cq_np_req ( pcie_cq_np_req ), .pcie_cq_np_req_count ( pcie_cq_np_req_count ), .cfg_phy_link_down ( cfg_phy_link_down ), .cfg_phy_link_status ( cfg_phy_link_status), .cfg_negotiated_width ( cfg_negotiated_width ), .cfg_current_speed ( cfg_current_speed ), .cfg_max_payload ( cfg_max_payload ), .cfg_max_read_req ( cfg_max_read_req ), .cfg_function_status ( cfg_function_status ), .cfg_function_power_state ( cfg_function_power_state ), .cfg_vf_status ( cfg_vf_status ), .cfg_vf_power_state ( cfg_vf_power_state ), .cfg_link_power_state ( cfg_link_power_state ), // Error Reporting Interface .cfg_err_cor_out ( cfg_err_cor_out ), .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), .cfg_err_fatal_out ( cfg_err_fatal_out ), .cfg_local_error_out ( cfg_local_error_out ), .cfg_local_error_valid ( cfg_local_error_valid ), .cfg_ltssm_state ( cfg_ltssm_state ), .cfg_rx_pm_state ( cfg_rx_pm_state ), .cfg_tx_pm_state ( cfg_tx_pm_state ), .cfg_rcb_status ( cfg_rcb_status ), .cfg_obff_enable ( cfg_obff_enable ), .cfg_pl_status_change ( cfg_pl_status_change ), .cfg_tph_requester_enable ( cfg_tph_requester_enable ), .cfg_tph_st_mode ( cfg_tph_st_mode ), .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), // /* agan add @ 20220603, for debug*/ // .cfg_msg_received ( cfg_msg_received ) , // .cfg_msg_received_data ( cfg_msg_received_data ), // .cfg_msg_received_type ( cfg_msg_received_type ), // // //-------------------------------------------------------------------------------// // EP Only // //-------------------------------------------------------------------------------// // Interrupt Interface Signals .cfg_interrupt_int ( cfg_interrupt_int ), .cfg_interrupt_pending ( {2'b0,cfg_interrupt_pending} ), .cfg_interrupt_sent ( cfg_interrupt_sent ), .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status [31:0]), .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), .cfg_interrupt_msi_pending_status_function_num (2'b0), .cfg_interrupt_msi_pending_status_data_enable (1'b0), .cfg_interrupt_msi_function_number (8'b0 ), //--------------------------------------------------------------------------------------// // System(SYS) Interface // //--------------------------------------------------------------------------------------// .sys_clk ( sys_clk ), .sys_clk_gt ( sys_clk_gt ), .sys_reset ( sys_reset_n ) ); end endgenerate // IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_reset_n)); //IBUFDS_GTE3 refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n)); //--------------------------------------------------------------------------------------------------------------------// // Instantiate Configurator design //--------------------------------------------------------------------------------------------------------------------// cgator #( .TCQ ( TCQ ), .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE), .EXTRA_PIPELINE ( EXTRA_PIPELINE ), .ROM_SIZE ( ROM_SIZE ), .ROM_FILE ( ROM_FILE ), .REQUESTER_ID ( REQUESTER_ID ), .C_DATA_WIDTH ( C_DATA_WIDTH ), .KEEP_WIDTH ( KEEP_WIDTH ) ) cgator_i ( // globals .user_clk ( user_clk_out ), .reset ( user_reset_out ), // User interface for configuration .start_config ( start_config ), .finished_config ( finished_config ), .failed_config ( failed_config ), // Rport AXIS interfaces .rport_s_axis_rq_tready ( rport_s_axis_rq_tready[0]), .rport_s_axis_rq_tdata ( rport_s_axis_rq_tdata ), .rport_s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ), .rport_s_axis_rq_tuser ( rport_s_axis_rq_tuser ), .rport_s_axis_rq_tlast ( rport_s_axis_rq_tlast ), .rport_s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ), .rport_m_axis_rc_tdata ( rport_m_axis_rc_tdata ), .rport_m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ), .rport_m_axis_rc_tlast ( rport_m_axis_rc_tlast ), .rport_m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ), .rport_m_axis_rc_tready ( rport_m_axis_rc_tready ), .rport_m_axis_rc_tuser ( rport_m_axis_rc_tuser ), // User AXIS interfaces .usr_s_axis_rq_tready ( s_axis_rq_tready ), .usr_s_axis_rq_tdata ( s_axis_rq_tdata ), .usr_s_axis_rq_tkeep ( s_axis_rq_tkeep ), .usr_s_axis_rq_tuser ( s_axis_rq_tuser ), .usr_s_axis_rq_tlast ( s_axis_rq_tlast ), .usr_s_axis_rq_tvalid ( s_axis_rq_tvalid ), .usr_m_axis_rc_tdata ( m_axis_rc_tdata ), .usr_m_axis_rc_tkeep ( m_axis_rc_tkeep ), .usr_m_axis_rc_tlast ( m_axis_rc_tlast ), .usr_m_axis_rc_tvalid ( m_axis_rc_tvalid ), .usr_m_axis_rc_tuser ( m_axis_rc_tuser ), .usr_m_axis_rc_tready ( m_axis_rc_tready ) // Rport CFG interface // User CFG interface // Rport PL interface ); //--------------------------------------------------------------------------------------------------------------------// endmodule // cgator_wrapper 这是cgator_wrapper的文件,ila核应该怎么配置?
08-07
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