计算机组成实验-第6章_CPU控制器设计

本次试验就是一个组合电路，讲指令中的信号转换喂数据通路的控制信号。
`timescale 1ns / 1ps
/*
输入为MIPS指令中的最高六位，op域。
根据这六位输入，产生九位输出，用以控制数据通路的各个部分。
将九个输出对应到八个led灯管和数码管中的一个小数点。
*/
module SingleCtrl(clk,OP,ALUop,RegDst,RegWrite,Branch,MemtoReg,MemRead,MemWrite,ALUsrc,led,digit_anode,segment);
input clk;
input wire [5:0] OP;//指令的高六位
output wire [1:0]ALUop;
output wire RegDst,RegWrite,Branch,MemtoReg,MemRead,MemWrite,ALUsrc;
output [3:0] digit_anode;
output [7:0] segment;
output [7:0] led;
wire R,LW,SW,BEQ;
assign R = ~OP[0] & ~OP[1] & ~OP[2] & ~OP[3] & ~OP[4] & ~OP[5];
assign LW = OP[0] & OP[1] & ~OP[2] & ~OP[3] & ~OP[4] & OP[5];
assign SW = OP[0] & OP[1] & ~OP[2] & OP[3] & ~OP[4] & OP[5];
assign BEQ = ~OP[0] & ~OP[1] & OP[2] & ~OP[3] & ~OP[4] & ~OP[5];
assign RegDst = R;
assign ALUsrc = LW | SW;
assign MemtoReg = LW;
assign RegWrite = R | LW;
assign MemRead = LW;
assign MemWrite = SW;
assign Branch = BEQ;
assign ALUop = {R, BEQ};
display I0(clk,ALUop,RegDst,RegWrite,Branch,MemtoReg,MemRead,MemWrite,ALUsrc,digit_anode,led,segment);
endmodule
//display 模块
module 
display(clk,ALUop,RegDst,RegWrite,Branch,MemtoReg,MemRead,MemWrite,ALUsrc,digit_anode,led,segment);
input clk;
input wire [1:0] ALUop;
input wire RegDst,RegWrite,Branch,MemtoReg,MemRead,MemWrite,ALUsrc;
output reg [3:0] digit_anode;
output reg [7:0] segment;
output [7:0] led;
assign led[7]=ALUsrc;
assign led[6]=MemtoReg;
assign led[5]=RegWrite;
assign led[4]=MemRead;
assign led[3]=MemWrite;
assign led[2]=Branch;
assign led[1]=ALUop[1];
assign led[0]=ALUop[0];
always@(posedge clk)
begin
digit_anode <= 4'b0111;
if(RegDst==1)
begin
segment <= 8'b01111111;
end
else 
segment <= 8'b11111111;
end
endmodule



`timescale 1ns / 1ps
module test;

     // Inputs
     reg clk;
     reg [5:0] OP;

     // Outputs
     wire [1:0] ALUop;
     wire RegDst;
     wire RegWrite;
     wire Branch;
     wire MemtoReg;
     wire MemRead;
     wire ALUsrc;
     wire [7:0] led;
     wire [3:0] digit_anode;
     wire [7:0] segment;

     // Instantiate the Unit Under Test (UUT)
     SingleCtrl uut (
          .clk(clk),
          .OP(OP),
          .ALUop(ALUop),
          .RegDst(RegDst),
          .RegWrite(RegWrite),
          .Branch(Branch),
          .MemtoReg(MemtoReg),
          .MemRead(MemRead),
          .ALUsrc(ALUsrc),
          .led(led),
          .digit_anode(digit_anode),
          .segment(segment)
     );

     always begin
          clk=~clk;
          #10;
     end
     initial begin
          // Initialize Inputs
          clk = 0;
          OP = 0;

          // Wait 100 ns for global reset to finish
          #100;
       
          // Add stimulus here
          OP=0;
          #200;
          OP=35;
          #200;
          OP=43;
          #200;
          OP=4;
          #200;
          $stop;
     end
     
endmodule






NET "clk" LOC="T9";
NET "digit_anode[0]" LOC = "d14" ;
NET "digit_anode[1]" LOC = "g14" ;
NET "digit_anode[2]" LOC = "f14" ;
NET "digit_anode[3]" LOC = "e13" ;
NET "segment[0]" LOC="E14";
NET "segment[1]" LOC="G13";  
NET "segment[2]" LOC="N15";
NET "segment[3]" LOC="P15";
NET "segment[4]" LOC="R16";
NET "segment[5]" LOC="F13";
NET "segment[6]" LOC="N16";
NET "segment[7]" LOC="P16";
NET "OP[0]" LOC="F12";
NET "OP[1]" LOC="G12";
NET "OP[2]" LOC="H14";
NET "OP[3]" LOC="H13";
NET "OP[4]" LOC="J14";
NET "OP[5]" LOC="J13";
NET "led[0]" LOC="K12";
NET "led[1]" LOC="P14";
NET "led[2]" LOC="L12";
NET "led[3]" LOC="N14";
NET "led[4]" LOC="P13";
NET "led[5]" LOC="N12";
NET "led[6]" LOC="P12";
NET "led[7]" LOC="P11";