本文详细介绍了标准编程序列，用于启动 IDE DMA 设备与内存之间的总线主机数据传输过程。主要包括准备 PRD 表、设置 PRD 表指针寄存器、发送 DMA 命令、启动总线主机功能、响应数据传输请求、处理传输结束中断等步骤。
3.1. Standard Programming Sequence
To initiate a bus master transfer between memory and an IDE DMA slave device, the following steps are
required:
1) Software prepares a PRD Table in system memory. Each PRD is 8 bytes long and consists of an
address pointer to the starting address and the transfer count of the memory buffer to be
transferred. In any given PRD Table, two consecutive PRDs are offset by 8-bytes and are aligned
on a 4-byte boundary.
2) Software provides the starting address of the PRD Table by loading the PRD Table Pointer
Register . The direction of the data transfer is specified by setting the Read/Write Control bit.
Clear the Interrupt bit and Error bit in the Status register.
3) Software issues the appropriate DMA transfer command to the disk device.
4) Engage the bus master function by writing a '1' to the Start bit in the Bus Master IDE Command
Register for the appropriate channel.
5) The controller transfers data to/from memory responding to DMA requests from the IDE device.
6) At the end of the transfer the IDE device signals an interrupt.
7) In response to the interrupt, software resets the Start/Stop bit in the command register. It then
reads the controller status and then the drive status to determine if the transfer completed
successfully.
To initiate a bus master transfer between memory and an IDE DMA slave device, the following steps are
required:
1) Software prepares a PRD Table in system memory. Each PRD is 8 bytes long and consists of an
address pointer to the starting address and the transfer count of the memory buffer to be
transferred. In any given PRD Table, two consecutive PRDs are offset by 8-bytes and are aligned
on a 4-byte boundary.
2) Software provides the starting address of the PRD Table by loading the PRD Table Pointer
Register . The direction of the data transfer is specified by setting the Read/Write Control bit.
Clear the Interrupt bit and Error bit in the Status register.
3) Software issues the appropriate DMA transfer command to the disk device.
4) Engage the bus master function by writing a '1' to the Start bit in the Bus Master IDE Command
Register for the appropriate channel.
5) The controller transfers data to/from memory responding to DMA requests from the IDE device.
6) At the end of the transfer the IDE device signals an interrupt.
7) In response to the interrupt, software resets the Start/Stop bit in the command register. It then
reads the controller status and then the drive status to determine if the transfer completed
successfully.
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