Low byte reference in intel 64

最新推荐文章于 2023-04-21 23:18:44 发布

Cloud_Apex

最新推荐文章于 2023-04-21 23:18:44 发布

阅读量1.9k

点赞数

CC 4.0 BY-SA版权

文章标签： reference byte

本文链接：https://blog.youkuaiyun.com/Cloud_Apex/article/details/1474067

本文探讨了64位模式下处理器对于字节寄存器访问的限制。具体而言，指令不能同时引用传统高位字节（如AH、BH、CH、DH）与新的字节寄存器，但可以同时引用传统低位字节（如AL、BL、CL、DL）与新的字节寄存器。此外，体系结构通过将高位字节引用转换为低位字节引用来实施这些限制。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

In 64-bit mode, there are limitations on accessing byte registers. An instruction cannot reference legacy high-bytes (for example: AH, BH, CH, DH) and one of the new byte registers at the same time (for example: the low byte of the RAX register). However, instructions may reference legacy low-bytes (for example: AL, BL, CL or
DL) and new byte registers at the same time (for example: the low byte of the R8 register, or RBP). The architecture enforces this limitation by changing high-byte references (AH, BH, CH, DH) to low byte references (BPL, SPL, DIL, SIL: the low 8 bits for RBP, RSP, RDI and RSI) for instructions using a REX prefix.