SystemC自带example的cpu之Data Cache研习

        例子中并没有数据缓冲的体现，和指令缓冲一样，仅仅就是RAM的读写设计。上来先是对RAM内容进行初始化，然后就是根据输入的使能信号和读写地址，直接进行相应的操作了。

struct dcache : sc_module { 
    sc_in<signed> 		datain; 	// input data
    sc_in<unsigned>  	statein; 	// input state bit MESI(=3210)
    sc_in<bool>  		cs;    		// chip select
    sc_in<bool>  		we;    		// write enable 
    sc_in<unsigned >  	addr;  		// address
    sc_in<unsigned>  	dest;    	// write back to which register

    sc_out<unsigned>  	destout;    // write back to which register
    sc_out<signed>  	dataout;  	// dataram data out
    sc_out<bool>  		out_valid;  // output valid
    sc_out<unsigned>  	stateout;  	// state output
    sc_in_clk 		CLK;

    // Parameter
    unsigned *dmemory;	 				// data memory
    unsigned *dsmemory;	 				// data state memory
    unsigned *dtagmemory;	 		    // tag memory
    int wait_cycles; 					// cycles # it takes to