cauchy911的专栏

安全第一嵌入式C规范，为众多的大汽车厂家所遵循，搞实际嵌入式工程项目的人员必读！

MISRC1998版，经典！对于做嵌入式C开发的人员来说，应该说是必须的！

Xilinx公司CPLD的应用手册！适合工程应用参考！

Xilinx ISE 11.1 破解文件，绝对好用！快来下！Xilinx ISE 11.1 破解文件，绝对好用！Xilinx ISE 11.1 破解文件，绝对好用！

Modbus总线协议，可以用于组建RS485总线网络通信，关于Modbus总线协议的详细介绍！

In the two decades since field-programmable gate arrays (FPGAs) were introduced, they have radically changed the way digital logic is designed and deployed. By marrying the high performance of application-specific integrated circuits (ASICs) and the flexibility of microprocessors, FPGAs have made possible entirely new types of applications. This has helped FPGAs supplant both ASICs and digital signal processors (DSPs) in some traditional roles. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. Thus, an FPGA user must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic.

The purpose of this application note is to describe the main elements of an RS-422 and RS-485 system. This application note attempts to cover enough technical details so that the system designer will have considered all the important aspects in his data system design. Since both RS-422 and RS- 485 are data transmission systems that use balanced differential signals, it is appropriate to discuss both systems in the same application note. Throughout this application note the generic terms of RS-422 and RS-485 will be used to represent the EIA/TIA-422 and EIA/TIA-485 Standards.

经典的数据通道设计入门教程 Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.

数字电路设计经典！ Writing testbench is as complex as writing the RTL code itself. This days ASIC's are getting more and more complex and thus the challenge to verify this complex ASIC. Typically 60-70% of time in any ASIC is spent on verification/validation/testing. Even though above facts are well know to most of the ASIC engineers, but still engineers think that there is no glory in verification.