| An interrupt is usually defined as an event that alters the sequence of instructions executed by a processor | ||||||||||
| are often divided into synchronous and asynchronous interrupts : | ||||||||||
| · Synchronous interrupts are produced by the CPU control unit | ||||||||||
| while executing instructions and are called synchronous | ||||||||||
| because the control unit issues them only after terminating the execution of an instruction | ||||||||||
| · Asynchronous interrupts are generated by other hardware devices | ||||||||||
| at arbitrary times with respect to the CPU clock signals | ||||||||||
| Exceptions, on the other hand, are caused either by programming errors or | ||||||||||
| by anomalous conditions that must be handled by the kernel | ||||||||||
| Interrupt handling is one of the most sensitive tasks performed by the kernel, | ||||||||||
| because it must satisfy the following constraints: | ||||||||||
| 1,The activities that the kernel needs to perform in response to an interrupt | ||||||||||
| are thus divided into a critical urgent part that the kernel executes right away and a deferrable part that is left for later | ||||||||||
| 2,Because interrupts can come anytime, | ||||||||||
| the kernel might be handling one of them while another one (of a different type) occurs | ||||||||||
| the interrupt handlers must be coded so that the corresponding kernel control paths can be executed in a nested manner | ||||||||||
| 3,Although the kernel may accept a new interrupt signal while handling a previous one, | ||||||||||
| some critical regions exist inside the kernel code where interrupts must be disabled | ||||||||||
| The Intel documentation classifies interrupts and exceptions as follows: | ||||||||||
| · Interrupts: | ||||||||||
| Maskable interrupts | ||||||||||
| Nonmaskable interrupts | ||||||||||
| A maskable interrupt can be in two states: masked or unmasked; | ||||||||||
| a masked interrupt is ignored by the control unit as long as it remains masked | ||||||||||
| Only a few critical events (such as hardware failures) give rise to nonmaskable interrupts . | ||||||||||
| Nonmaskable interrupts are always recognized by the CPU | ||||||||||
| · · Exceptions: | ||||||||||
| These are further divided into three groups, | ||||||||||
| depending on the value of the eip register | ||||||||||
| that is saved on the Kernel Mode stack when the CPU control unit raises the exception | ||||||||||
| Faults | ||||||||||
| Can generally be corrected | ||||||||||
| The saved value of eip is the address of the instruction that caused the fault | ||||||||||
| Traps | ||||||||||
| The saved value of eip is the address of the instruction that should be executed after the one that caused the trap | ||||||||||
| A trap is triggered only when there is no need to reexecute the instruction that terminated | ||||||||||
| Aborts | ||||||||||
| A serious error occurred; the control unit is in trouble, | ||||||||||
| and it may be unable to store in the eip register the precise location of the instruction causing the exception | ||||||||||
| Aborts are used to report severe errors, such as hardware failures and invalid or inconsistent values in system tables | ||||||||||
| Programmed exceptions | ||||||||||
| Occur at the request of the programmer. They are triggered by int or int3 instructions | ||||||||||
| Each interrupt or exception is identified by a number ranging from 0 to 255; | ||||||||||
| Intel calls this 8-bit unsigned number a vector. The vectors of nonmaskable interrupts and exceptions are fixed, | ||||||||||
| while those of maskable interrupts can be altered by programming the Interrupt Controller | ||||||||||
Understanding the linux kernel-ch4-Interrupts and Exceptions
最新推荐文章于 2021-08-17 19:59:48 发布
本文介绍了计算机系统中中断和异常的概念及分类,包括同步与异步中断的区别,以及可屏蔽和不可屏蔽中断的特点。同时探讨了中断处理过程中的关键挑战与约束条件,并详细解释了故障、陷阱和中止等不同类型的异常。
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