数字电路设计之m0仿真结果

最新推荐文章于 2021-06-04 14:30:17 发布

Snail_Walker

最新推荐文章于 2021-06-04 14:30:17 发布

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分类专栏： Digital Chip Design

本文链接：https://blog.youkuaiyun.com/c602273091/article/details/40371353

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仿真结果如下：

仿真代码：

enable <= 1; start <= 0; i_datain <= 0; d_datain <= 0;
        #10 reset <= 0;
       #10 reset <= 1;
       #10 enable <= 1;
       #10 start <= 1;
       // Add stimulus here
       #10 i_datain <= { `LDR1, 5'b0000_1, `gr0,`gr1};      //LDR0 5'b01001,PC                00:4a01
        #10 i_datain <= { `LDR1, 5'b0001_0,`gr0,`gr2};      //LDR0 5'b01001,PC                    04:4902
       //#10; //阻塞相当于延迟一个周期取i_datain
        #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
        //#10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
       //     d_datain <=   RAM[0];//32'hffff0000;//32'h000f0000;
        #10 //i_datain <= { `ADD1, `gr2, `gr0, `gr3};                                        //08:1883
           i_datain <= { `SUB0, `gr1, `gr2, `gr1};
              d_datain <=   RAM[0];//32'hffff0000;//32'h000f0000;
       //   d_datain <=   RAM[1];//32'h00ff10AB;//32'h00000004;

      //#10 i_datain <= { `SUB0, `gr2, `gr1, `gr1};        //ADD1 7'b0001100 //gr1=gr1-gr2   0c:1a89
                 //d_datain <=   RAM[1];
       //below
       #10 i_datain <= { `B1, 12'b0100_0000_1001 };                                           //0e:d411
                d_datain <=   RAM[1];
       #10 i_datain <= { `B1, 12'b0010_0000_0010 };                                           //10:d802
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
        #10 i_datain <= { `SUB0, `gr1, `gr2, `gr1};
       #10 i_datain <= { `B1, 12'b0100_0000_1001 };                                           //0e:d411
        // d_datain <=   RAM[1];
       #10 i_datain <= { `B1, 12'b0010_0000_0010 };                                         //10:d802
       #10 i_datain <= { `MOV0,8'b00010001};                                                //14:4611
       #10 i_datain <= { `MOV0,8'b00011010};                                                //18:461a
       #10 i_datain <= { `B0,11'b00000000010};                                              //1c:e002
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
        #10 i_datain <= { `SUB0, `gr1, `gr2, `gr1};
       #10 i_datain <= { `B1, 12'b010000001001 };                                           //0e:d411
           // d_datain <=   RAM[1];
       #10 i_datain <= { `B1, 12'b001000000010 };                                           //10:d802
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
       #10 i_datain <= { `ADD1, `gr1, `gr0, `gr3};//ADD1 7'b0001100 //Rd=Rm+Rn                08:1883
        #10 i_datain <= { `SUB0, `gr1, `gr2, `gr1};
       #10 i_datain <= { `B1, 12'b010000001001 };                                           //0e:d411
          // d_datain <=   RAM[1];
       #10 i_datain <= { `SUB0, `gr1, `gr2, `gr1};                                          //nothing
       #10 i_datain <= { `SUB0, `gr1, `gr2, `gr1};                                          //nothing
       #10 i_datain <= { `STR0,11'b00011000010};                                            //1e:60c2
       #10 i_datain <= { `LDR1,5'b00001,`gr0,`gr1};                                         //20:6841
              //d_datain <=   RAM[0];
       #10 i_datain <= { `LDR1,5'b00010,`gr0,   `gr2};                                        //24:6882
              //d_datain <=   RAM[1];
       #10 i_datain <= { `ADD4,`gr4,8'b00000001};                                           //28:3401
            //d_datain <=   RAM[1];
       #10 i_datain <= { `SUB0,`gr2,`gr3,`gr2};                                             //2c:1ad2
              d_datain <=   RAM[0];
       #10 i_datain <= { `B1,4'b1000,8'b00010000};
                d_datain <=   RAM[1];       //2e:d810
       #10 i_datain <= { `B0,11'b00000001100};                                              //30:e010
       //#10

                 i_datain <= { `ADD4,`gr4,8'b00000001};                                           //28:3401
       #10 i_datain <= { `ADD4,`gr4,8'b00000001};                                           //28:3401
       #10 i_datain <= { `ADD4,`gr4,8'b00000001};                                           //28:3401
       #10 i_datain <= { `SUB0,`gr2,`gr3,`gr2};                                             //2c:1ad2
       #10 i_datain <= { `B1,4'b0100,8'b00010000};                                          //2e:d810
       #10 i_datain <= { `SUB2,`gr4,8'b00000001};                                           //34:3c01 nothing
       #10 i_datain <= { `SUB2,`gr4,8'b00000001};                                           //34:3c01 nothing
       #10 i_datain <= { `SUB2,`gr4,8'b00000001};                                           //34:3c01
       #10 i_datain <= { `B1,4'b1000,8'b00010100};                                          //38:d814
       #10 i_datain <= { `ADD1,`gr5,`gr1,`gr5};                                             //3c:194d
       #10 i_datain <= { `B0,11'b000_0001_0000};                                            //3e:1910
       #10 i_datain <= { `SUB2,`gr4,8'b00000001};                                           //34:3c01
       #10 i_datain <= { `SUB2,`gr4,8'b00000001};                                           //34:3c01 nothing
       #10 i_datain <= { `B1,4'b1000,8'b00010100};                                          //38:d814
       #10 i_datain <= { `ADD1,`gr5,`gr1,`gr5};                                             //3c:194d
       #10 i_datain <= { `B0,11'b000_0001_0000};                                            //3e:1910
       #10 i_datain <= { `SUB2,`gr4,8'b00000001};                                           //34:3c01
       #10 i_datain <= { `SUB2,`gr4,8'b00000001};                                           //34:3c01
       #10 i_datain <= { `B1,4'b1000,8'b00010100};                                          //38:d814
       #10 i_datain <= { `STR0,5'b00101,`gr0,`gr5};                                         //40:6105
       //#50
       #100
       $finish;