bgskip的博客

module top_module ( input clk, input reset, // Synchronous reset input s, input w, output z ); parameter A=0, B=1; reg state, next; always@(posedge clk)begin if(reset) state <= A; else

module top_module ( input clk, input areset, input x, output z ); parameter [1:0] a=0, b=1, c=2; reg [2:0] state, next; always@(posedge clk or posedge areset)begin if(areset) state <= a; else state <= next; end always@(*)beg