/*
Copyright © HiSilicon
(Shanghai
) Technologies Co., Ltd. 2020-2023. All rights reserved.
Description: board src
Author: hsan
Create: 2020-6-30
History:
*/
#include <common.h>
#include <cpu_func.h>
#include <clk.h>
#include <mtd.h>
#include <nand.h>
#include <reset.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/system.h>
#include <dm/uclass-internal.h>
#include <asm/global_data.h>
#include <asm/sections.h>
#include <env.h>
#include <env_internal.h>
#include <asm/cache.h>
#include <linux/sizes.h>
#include <linux/delay.h>
#include “securec.h”
#include “hi_bit.h”
#include “hi_comdef.h”
#include “hi_types.h”
#include “hi_errno.h”
#include “hi_register.h”
#include “hi_crg.h”
#include “hi_fmc.h”
#include “hi_spi_nor.h”
#include “hi_get_rstinfo.h”
#include “hi_load_fip.h”
#include “hi_gic.h”
#include “hi_board_id.h”
#include “hi_ledpwm.h”
DECLARE_GLOBAL_DATA_PTR;
#define HI_GLB_CTL_RB_INDEX 4
#define HI_UBOOT_RST_INFO 2
#define CLEAR_BIT 0
#define CHECK_VAL 0xa
#define HI_GEPHY_MDIO_MUX_REG 0x1012B40C
#define HI_FST_S_SRST_GEPHY_REG 0x11819448
#define HI_FST_S_GATE_EN_GEPHY_REF_REG 0x11819214
#define HI_EXTPHY_GROUP_SEL_REG 0x1012b910
#define HI_CFG_EXTPHY1_REFCLK_MOD_REG 0x11916010
#define HI_CFG_EXTPHY1_MDC_MOD_REG 0x11916014
#define HI_CFG_EXTPHY1_MDIO_MOD_REG 0x11916018
#define HI_IOMG_REG_
BASE { 0x11815000, 0x11915000, 0x11915014, 0x11916000, 0x11917000 }
#define HI_IOMG_REG_SIZE { 0x34, 0x10, 0x28, 0x1C, 0x20 }
#define HI_IOMG_REG_NUM 5
#define HI_RESET_GPIOS_PROPERTY_LEN 3
#define HI_IPIO_ISO_EN_REG 0x182002a0
#define HI_FST_S_PLL_ISO_CTRL_REG 0x118190fc
#define HI_FST_N_PLL_ISO_CTRL_REG 0x1191b0fc
#define HI_FST_N_PLL_EXT_BYPASS_REG 0x1191b1f4
#define HI_FST_N_XTAL_CLK_SEL_REG 0x1191b1f0
#define HI_FST_N_PLSW_CLK_MODE_SEL_REG 0x1191b804
#define HI_PLSW_SC_GATE_EN_REG 0x14980024
#define HI_FST_N_FREQ_CTRL_FM_REG 0x1191b704
#define HI_FST_N_FREQ_CTRL_PFE_REG 0x1191b708
#define HI_FST_N_FREQ_CTRL_DP_REG 0x1191b70c
#define HI_ITF_CLK_EN_REG 0x14001020
#define HI_ITF_CLK_EN1_REG 0x51001020
#define HI_NNI_SOFT_RESET_REG 0x51001018
#define HI_POCFG_REG 0x1012b180
#define HI_TCXO_RCD_SET_96M 0x0
#define HI_MSK_BIT0 0x1
#define HI_MSK_BIT1 0x2
#define HI_MSK_BIT3 0x8
#define HI_MSK_BIT4 0x10
#define HI_MSK_BIT5 0x20
#define HI_MSK_BIT01 0x3
#define HI_MSK_BIT02 0x7
#define HI_MSK_BIT_ALL 0xffffffff
#define TZPC_SEC 0x0
union hi_tzpc_ctrl1 {
struct {
uint32_t tzpc_prot_sysctrl : 1;
uint32_t tzpc_prot_pwm_ctrl : 1;
uint32_t tzpc_prot_hw_spi : 1;
uint32_t tzpc_prot_hw_voip : 1;
uint32_t tzpc_prot_bootrom : 1;
uint32_t tzpc_prot_dmac : 1;
uint32_t tzpc_prot_asc_hub : 1;
uint32_t tzpc_prot_fmc_sfr : 1;
uint32_t tzpc_prot_fmc_mem : 1;
uint32_t reserved : 23;
} bits;
uint32_t value;
};
union hi_tzpc_ctrl7 {
struct {
uint32_t fastio_n_efuse_tzpc_prot : 1;
uint32_t fastio_n_ioctrl_tzpc_prot : 1;
uint32_t fastio_n_nfc_tzpc_prot : 1;
uint32_t fastio_n_crg_tzpc_prot : 1;
uint32_t fastio_n_misc_tzpc_prot : 1;
uint32_t fastio_n_ups_phy_tzpc_prot : 1;
uint32_t fastio_n_usb2phy_tzpc_prot : 1;
uint32_t fastio_n_usb2ctrl_tzpc_prot : 1;
uint32_t fastio_n_pcie_phy_tzpc_prot : 1;
uint32_t fastio_n_usb_ahb_tzpc_prot : 1;
uint32_t reserved : 22;
} bits;
uint32_t value;
};
union hi_acp_port {
struct {
uint32_t comm_peri_aw_protect : 1;
uint32_t comm_peri_ar_protect : 1;
uint32_t reserved : 30;
} bits;
uint32_t value;
};
union hi_mst_port_ctrl2 {
struct {
uint32_t usb_n_awprot : 1;
uint32_t usb_n_arprot : 1;
uint32_t reserved : 30;
} bits;
uint32_t value;
};
union hi_mst_port_ctrl3 {
struct {
uint32_t pcie_n_awprot : 1;
uint32_t pcie_n_arprot : 1;
uint32_t reserved : 30;
} bits;
uint32_t value;
};
union hi_mst_port_ctrl7 {
struct {
uint32_t tzpc_ssi_awprot : 1;
uint32_t tzpc_ssi_arprot : 1;
uint32_t tzpc_fmc_awprot : 1;
uint32_t tzpc_fmc_arprot : 1;
uint32_t tzpc_usb_s_awprot : 1;
uint32_t tzpc_usb_s_arprot : 1;
uint32_t tzpc_fem_awprot : 1;
uint32_t tzpc_fem_arprot : 1;
uint32_t tzpc_pie_awprot : 1;
uint32_t tzpc_pie_arprot : 1;
uint32_t reserved : 22;
} bits;
uint32_t value;
};
void enable_caches
(void
)
{
if
(!icache_status
())
icache_enable
();
dcache_enable
();
}
void dram_
bank_mmu_setup
(int
bank)
{
struct bd_info *bd = gd->bd;
int i;
/* bd->bi_dram is available only after relocation */ if
((gd->flags & GD_FLG_RELOC
) == 0
) return; debug
("%s:
bank: %d\n", __func__,
bank); for
(i = bd->bi_dram[
bank].start >> MMU_SECTION_SHIFT; i <
(bd->bi_dram[
bank].start >> MMU_SECTION_SHIFT
) +
(bd->bi_dram[
bank].size >> MMU_SECTION_SHIFT
); i++
) set_section_dcache
(i, DCACHE_DEFAULT_OPTION | TTB_SECT_S_MASK
);
}
static void hi_do_clear_remap
(void
)
{
uint32_t regtmp;
ofnode sysctrl_node;
uintptr_t
addr;
sysctrl_node = ofnode_by_compatible
(ofnode_null
(), "hsan,sysctrl"
);
addr = ofnode_get_
addr_index
(sysctrl_node, 0
); hi_reg_read
(addr, regtmp
); regtmp |= HI_BIT08_1; hi_reg_write
(addr, regtmp
);
}
void hi_relocate_uboot
(void
)
{
int32_t ret;
ret = memcpy_s
((void *
)PHYS_SDRAM_1, SZ_512K,
(void *
)CONFIG_SYS_TEXT_
BASE, SZ_16K
);
if
(ret != EOK
) {
debug
(“hi_relocate_uboot::memcpy fail!\n”
);
return;
}
}
int arch_cpu_init
(void
)
{
return 0;
}
int board_early_init_f
(void
)
{
return 0;
}
int dram_init
(void
)
{
gd->ram_size =
PHYS_SDRAM_1_SIZE;
return 0;
}
static void set_fdt_
addr(void
)
{
if
(fdt_magic
(gd->fdt_blob
) != FDT_MAGIC
)
return;
env_set_hex
("fdt_
addr",
(ulong
)gd->fdt_blob
);
}
void verify_bootflag
(void
)
{
const char *bootflag;
bootflag = env_get
("bootflag"
); if
(bootflag &&
(!strcmp
(bootflag, "a"
) || !strcmp
(bootflag, "b"
))) { pr_info
("bootflag verify succ\n"
); } else { env_set
("bootflag", "a"
); pr_info
("invalid bootflag, using default\n"
); env_save
(); }
}
void restore_bootreg
(void
)
{
uint32_t bootreg;
uint32_t bootsel;
hi_reg_read
(UBOOT_SEL_REG, bootreg
); bootsel =
(bootreg & UBOOT_SEL_MASK
) >> UBOOT_SEL_SHIFT; if
(bootsel == UBOOTA_FLAG
) { bootreg &= ~UBOOT_SEL_MASK; bootreg |=
(UBOOTB_FLAG << UBOOT_SEL_SHIFT
); } else { bootreg &= ~UBOOT_SEL_MASK; bootreg |=
(UBOOTA_FLAG << UBOOT_SEL_SHIFT
); } hi_reg_write
(UBOOT_SEL_REG, bootreg
);
}
int misc_init_r
(void
)
{
set_fdt_
addr();
verify_bootflag
();
restore_bootreg
();
return 0;
}
#ifdef CONFIG_REVISION_TAG
u32 get_board_rev
(void
)
{
return 0x5652001;
}
#endif /* CONFIG_REVISION_TAG */
static void plsw_reg_set
(uint32_t reg_
addr, uint32_t mask, uint32_t value
)
{
uint32_t val;
hi_reg_read
(reg_
addr, val
);
val &= ~mask;
val |= value;
hi_reg_write
(reg_
addr, val
);
}
static void phy_clk_init
(void
)
{
uint32_t val = 0;
hi_reg_read
(HI_POCFG_REG, val
);
if
((val & HI_MSK_BIT5
) == HI_TCXO_RCD_SET_96M
)
plsw_reg_set
(HI_GEPHY_MDIO_MUX_REG, HI_MSK_BIT_ALL, 0x7
);
else
plsw_reg_set
(HI_GEPHY_MDIO_MUX_REG, HI_MSK_BIT_ALL, 0x5
);
plsw_reg_set
(HI_FST_S_GATE_EN_GEPHY_REF_REG, HI_MSK_BIT_ALL, 0x1
); plsw_reg_set
(HI_FST_S_SRST_GEPHY_REG, HI_MSK_BIT_ALL, 0x0
); udelay
(0xa
); // 10us plsw_reg_set
(HI_FST_S_SRST_GEPHY_REG, HI_MSK_BIT_ALL, 0x1
);
}
static void plsw_clk_init
(void
)
{
plsw_reg_set
(HI_IPIO_ISO_EN_REG, HI_MSK_BIT0, 0x0
);
plsw_reg_set
(HI_FST_S_PLL_ISO_CTRL_REG, HI_MSK_BIT0, 0x1
);
plsw_reg_set
(HI_FST_N_PLL_ISO_CTRL_REG, HI_MSK_BIT0, 0x1
);
plsw_reg_set
(HI_FST_N_PLL_EXT_BYPASS_REG, HI_MSK_BIT01, 0x3
);
plsw_reg_set
(HI_FST_N_XTAL_CLK_SEL_REG, HI_MSK_BIT01, 0x0
);
plsw_reg_set
(HI_FST_N_PLSW_CLK_MODE_SEL_REG, HI_MSK_BIT01, 0x0
);
plsw_reg_set
(HI_PLSW_SC_GATE_EN_REG, HI_MSK_BIT02, 0x0
);
plsw_reg_set
(HI_FST_N_FREQ_CTRL_FM_REG, HI_MSK_BIT4, 0x0
); plsw_reg_set
(HI_FST_N_FREQ_CTRL_FM_REG, HI_MSK_BIT01, 0x1
); // tiangong1 plsw_reg_set
(HI_FST_N_FREQ_CTRL_FM_REG, HI_MSK_BIT4, 0x1 << 0x4
); plsw_reg_set
(HI_FST_N_FREQ_CTRL_PFE_REG, HI_MSK_BIT4, 0x0
); plsw_reg_set
(HI_FST_N_FREQ_CTRL_PFE_REG, HI_MSK_BIT02, 0x7
); // tiangong1 plsw_reg_set
(HI_FST_N_FREQ_CTRL_PFE_REG, HI_MSK_BIT4, 0x1 << 0x4
); plsw_reg_set
(HI_FST_N_FREQ_CTRL_DP_REG, HI_MSK_BIT3, 0x0
); plsw_reg_set
(HI_FST_N_FREQ_CTRL_DP_REG, HI_MSK_BIT02, 0x7
); // tiangong1 plsw_reg_set
(HI_FST_N_FREQ_CTRL_DP_REG, HI_MSK_BIT3, 0x1 << 0x3
); plsw_reg_set
(HI_PLSW_SC_GATE_EN_REG, HI_MSK_BIT02, 0x7
); plsw_reg_set
(HI_ITF_CLK_EN_REG, HI_MSK_BIT_ALL, 0xffffffff
); plsw_reg_set
(HI_ITF_CLK_EN1_REG, HI_MSK_BIT_ALL, 0xffffffff
); plsw_reg_set
(HI_NNI_SOFT_RESET_REG, HI_MSK_BIT_ALL, 0xffffffff
); plsw_reg_set
(HI_FST_S_GATE_EN_GEPHY_REF_REG, HI_MSK_BIT0, 0x1
);
}
static void hi_mdio_init
(void
)
{
plsw_reg_set
(HI_EXTPHY_GROUP_SEL_REG, HI_MSK_BIT_ALL, 0x1
);
plsw_reg_set
(HI_CFG_EXTPHY1_REFCLK_MOD_REG, HI_MSK_BIT_ALL, 0x2
);
plsw_reg_set
(HI_CFG_EXTPHY1_MDC_MOD_REG, HI_MSK_BIT_ALL, 0x3
);
plsw_reg_set
(HI_CFG_EXTPHY1_MDIO_MOD_REG, HI_MSK_BIT_ALL, 0x2
);
}
static void hi_gpio_mode_cfg
(uint32_t gpio, uint32_t mode
)
{
uint32_t iomg_reg_
base[HI_IOMG_REG_NUM] = HI_IOMG_REG_
BASE;
uint32_t iomg_reg_size[HI_IOMG_REG_NUM] = HI_IOMG_REG_SIZE;
uint32_t i;
uint32_t gpio_begin = 0;
for
(i = 0; i < HI_IOMG_REG_NUM; i++
) { if
(gpio_begin <= gpio && gpio < gpio_begin + iomg_reg_size[i] / sizeof
(uint32_t
)) { plsw_reg_set
(iomg_reg_
base[i] +
(gpio - gpio_begin
) * sizeof
(uint32_t
), HI_MSK_BIT_ALL, mode
); return; } gpio_begin += iomg_reg_size[i] / sizeof
(uint32_t
); } pr_err
("gpio %d mode cfg error.\n", gpio
);
}
static void hi_extphy_rst_gpio_init
(void
)
{
ofnode node;
uint32_t reset_gpios[HI_RESET_GPIOS_PROPERTY_LEN] = { 0 };
node = ofnode_by_compatible
(ofnode_null
(), "ethernet-phy-ieee802.3-c45"
); while
(!ofnode_equal
(node, ofnode_null
())) { if
(ofnode_is_available
(node
) && ofnode_read_u32_array
(node, "reset-gpios", reset_gpios, HI_RESET_GPIOS_PROPERTY_LEN
) == 0
) { hi_gpio_mode_cfg
(reset_gpios[0x1], 0x1
); } node = ofnode_by_compatible
(node, "ethernet-phy-ieee802.3-c45"
); }
}
int32_t board_early_init_r
(void
)
{
hi_mdio_init
();
hi_extphy_rst_gpio_init
();
phy_clk_init
();
plsw_clk_init
();
return 0;
}
#ifndef CONFIG_BOOT_TEE
static void hi_tzpc_sec_init
(ofnode node, uintptr_t
base_
addr)
{
uint32_t offset;
union hi_acp_port acp_port_reg;
if
(ofnode_read_u32
(node, “sec-ctrl-tzpc0-offset”, &offset
) != 0
)
return;
hi_reg_write
(base_
addr + offset, 0x0
);
if
(ofnode_read_u32
(node, "acp-port-offset", &offset
) != 0
) return; hi_reg_read
(base_
addr + offset, acp_port_reg.value
); acp_port_reg.bits.comm_peri_aw_protect = TZPC_SEC; acp_port_reg.bits.comm_peri_ar_protect = TZPC_SEC; hi_reg_write
(base_
addr + offset, acp_port_reg.value
);
}
static void hi_tzpc_port_init
(ofnode node, uintptr_t
base_
addr)
{
uint32_t offset;
union hi_mst_port_ctrl2 mst_port_ctrl2_reg;
union hi_mst_port_ctrl3 mst_port_ctrl3_reg;
union hi_mst_port_ctrl7 mst_port_ctrl7_reg;
if
(ofnode_read_u32
(node, "mst-port-ctrl2-offset", &offset
) != 0
) return; hi_reg_read
(base_
addr + offset, mst_port_ctrl2_reg.value
); mst_port_ctrl2_reg.bits.usb_n_awprot = TZPC_SEC; mst_port_ctrl2_reg.bits.usb_n_arprot = TZPC_SEC; hi_reg_write
(base_
addr + offset, mst_port_ctrl2_reg.value
); if
(ofnode_read_u32
(node, "mst-port-ctrl3-offset", &offset
) != 0
) return; hi_reg_read
(base_
addr + offset, mst_port_ctrl3_reg.value
); mst_port_ctrl3_reg.bits.pcie_n_awprot = TZPC_SEC; mst_port_ctrl3_reg.bits.pcie_n_arprot = TZPC_SEC; hi_reg_write
(base_
addr + offset, mst_port_ctrl3_reg.value
); if
(ofnode_read_u32
(node, "mst-port-ctrl7-offset", &offset
) != 0
) return; hi_reg_read
(base_
addr + offset, mst_port_ctrl7_reg.value
); mst_port_ctrl7_reg.bits.tzpc_fmc_awprot = TZPC_SEC; mst_port_ctrl7_reg.bits.tzpc_fmc_arprot = TZPC_SEC; mst_port_ctrl7_reg.bits.tzpc_usb_s_awprot = TZPC_SEC; mst_port_ctrl7_reg.bits.tzpc_usb_s_arprot = TZPC_SEC; mst_port_ctrl7_reg.bits.tzpc_pie_awprot = TZPC_SEC; mst_port_ctrl7_reg.bits.tzpc_pie_arprot = TZPC_SEC; hi_reg_write
(base_
addr + offset, mst_port_ctrl7_reg.value
);
}
#endif
static void hi_tzpc_init
(void
)
{
#ifndef CONFIG_BOOT_TEE
ofnode node;
uintptr_t
base_
addr;
union hi_tzpc_ctrl1 ctrl1_reg;
union hi_tzpc_ctrl7 ctrl7_reg;
uint32_t offset;
node = ofnode_by_compatible
(ofnode_null
(), "hsan,tzpc"
);
base_
addr = ofnode_get_
addr(node
); if
(base_
addr == -1
) return; if
(ofnode_read_u32
(node, "tzpc-ctrl1-offset", &offset
)) return; hi_reg_read
(base_
addr + offset, ctrl1_reg.value
); ctrl1_reg.bits.tzpc_prot_fmc_sfr = TZPC_SEC; ctrl1_reg.bits.tzpc_prot_fmc_mem = TZPC_SEC; hi_reg_write
(base_
addr + offset, ctrl1_reg.value
); if
(ofnode_read_u32
(node, "tzpc-ctrl7-offset", &offset
)) return; hi_reg_read
(base_
addr + offset, ctrl7_reg.value
); ctrl7_reg.bits.fastio_n_usb2phy_tzpc_prot = TZPC_SEC; ctrl7_reg.bits.fastio_n_usb2ctrl_tzpc_prot = TZPC_SEC; ctrl7_reg.bits.fastio_n_pcie_phy_tzpc_prot = TZPC_SEC; ctrl7_reg.bits.fastio_n_usb_ahb_tzpc_prot = TZPC_SEC; hi_reg_write
(base_
addr + offset, ctrl7_reg.value
); hi_tzpc_sec_init
(node,
base_
addr); hi_tzpc_port_init
(node,
base_
addr);
#endif
}
int board_init
(void
)
{
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
hi_initr_crg
();
hi_tzpc_init
();
plsw_reg_set
(0x11916010, HI_MSK_BIT_ALL, 0x3
); return HI_RET_SUCC;
}
static void hi_ledpwm_init
(void
)
{
plsw_reg_set
(0x11916014, HI_MSK_BIT_ALL, 0x3
);
plsw_reg_set
(0x119149a8, HI_MSK_BIT_ALL, 0x3
);
struct ledpwm_device *ledpwm_device;
struct ledpwm_state ledpwm_state;
int32_t chip_id = 0, channel_id = 1;
uint8_t steptable[STEPTABLE_LEN] = {
0,0,0,0,255,255,255,255,0,0,0,0,255,255,255,255,0,0,0,0,255,255,255,255,0,0,0,0,255,255,255,255,
0,0,0,0,255,255,255,255,0,0,0,0,255,255,255,255,0,0,0,0,255,255,255,255,0,0,0,0,255,255,255,255
};
ledpwm_device = ledpwm_get_device
(chip_id, channel_id
);
ledpwm_state = ledpwm_get_state
(ledpwm_device
);
ledpwm_disable
(ledpwm_device
);
ledpwm_state.mode = LOOP_MODE;
ledpwm_state.polarity = LEDPWM_POLARITY_NORMAL;
ledpwm_state.stepsize = 1;
memcpy_s
(ledpwm_state.steptable, STEPTABLE_LEN, steptable, STEPTABLE_LEN
);
ledpwm_state.enabled = LEDPWM_ENABLE;
ledpwm_apply_state
(ledpwm_device, &ledpwm_state
);
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init
(void
)
{
hi_do_clear_remap
();
hi_relocate_uboot
();
hi_gic_drv_register
();
//hi_ledpwm_init
();
#ifdef CONFIG_UBOOT_DRIVERS_GETRSTINFO
hi_initr_rstinfo
();
#endif
return 0;
}
#endif
#ifdef CONFIG_LAST_STAGE_INIT
int last_stage_init
(void
)
{
return 0;
}
#endif
#if defined
(CONFIG_HW_WATCHDOG
)
__weak void hw_watchdog_reset
(void
)
{
return;
}
__weak void hw_watchdog_init
(void
)
{
return;
}
#endif
void reset_cpu
(void
)
{
ofnode node;
uintptr_t glb_ctl_
addr;
uint32_t softrst_offset;
uint32_t softrst_val0;
uint32_t softrst_val1;
#ifdef CONFIG_UBOOT_DRIVERS_GETRSTINFO
uint32_t record_
addr;
rstinfo_reg rstinfo_value;
#endif
node = ofnode_by_compatible
(ofnode_null
(), "hsan,crg"
); glb_ctl_
addr = ofnode_get_
addr_index
(node, HI_GLB_CTL_RB_INDEX
); ofnode_read_u32
(node, "softrst_offset", &softrst_offset
); ofnode_read_u32
(node, "softrst_val0", &softrst_val0
); ofnode_read_u32
(node, "softrst_val1", &softrst_val1
);
#ifdef CONFIG_UBOOT_DRIVERS_GETRSTINFO
node = ofnode_by_compatible
(ofnode_null
(), “hsan,rstinfo”
);
if
(ofnode_valid
(node
)) {
ofnode_read_u32
(node, “record_
addr”, &record_
addr);
hi_reg_read
((uintptr_t
)record_
addr, rstinfo_value.val
); rstinfo_value.bits.soft_rst = HI_UBOOT_RST_INFO; rstinfo_value.bits.hard_dog_or_key_rst = CLEAR_BIT; hi_reg_write
((uintptr_t
)record_
addr, rstinfo_value.val
); }
#endif
printf
("reset_cpu\n"
); hi_reg_write
(glb_ctl_
addr + softrst_offset, softrst_val0
); hi_reg_write
(glb_ctl_
addr + softrst_offset, softrst_val1
); while
(1
);
}
#ifdef CONFIG_OF_LIBFDT_OVERLAY
/*
XOR the check value one by one to obtain the value of bits 0 to 3,
and compare it with the original value.
If they are the same, the board ID is returned. If they are different, the 0 is returned.
*/
uint32_t hi_read_board_id
(void
)
{
ofnode sysctrl_node;
uint32_t cnt, val, tmp, res;
uint32_t sysctrl_
base, boardid_offset;
sysctrl_node = ofnode_by_compatible
(ofnode_null
(), “hsan,sysctrl”
);
sysctrl_
base = ofnode_get_
addr(sysctrl_node
);
res = ofnode_read_u32
(sysctrl_node, “boardid-offset”, &boardid_offset
);
if
(res
) {
pr_err
(“no boardid-offset exists”
);
return 0;
}
hi_reg_read
(sysctrl_
base + boardid_offset, val
);
res =
(val & 0xF0000000
) >> 0x1c;
for
(cnt = 0x6; cnt > 0; cnt–
) {
tmp =
(val &
(0xf <<
(cnt * 0x4
))) >>
(cnt * 0x4
);
res = res ^ tmp;
}
res ^= CHECK_VAL;
if
((val & 0xf
) != res
) {
pr_err
(“read_board_id failed\n”
);
return 0;
}
return
(val & ~0xF0000000
);
}
#endif
针对以上代码，已经在“hi_ledpwm_init”中对GPIO31已经通过“plsw_reg_set
(0x11916014, HI_MSK_BIT_ALL, 0x3
)”进行了复用功能配置，为何还在要在“hi_mdio_init”中用“plsw_reg_set
(HI_CFG_EXTPHY1_MDC_MOD_REG, HI_MSK_BIT_ALL, 0x3
);”进行重复的复用配置，且kernel下GPIO32的LEDPWM电平不可控制，屏蔽掉这一行就可行了
需注意，plsw_reg_set
(0x11916014, HI_MSK_BIT_ALL, 0x3
)和plsw_reg_set
(HI_CFG_EXTPHY1_MDC_MOD_REG, HI_MSK_BIT_ALL, 0x3
)都是将GPIO32配置为LEDPWM功能。
这是为什么屏蔽掉这行kernel就行了？
本文详细解释了在U-Boot启动加载程序中使用的一个复杂的宏定义BANK_BASE(i)，该宏用于获取不同Flash存储器银行的基地址。通过示例说明了如何定义多个Flash设备及其基地址，并展示了GCC编译器支持的特殊语法。
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