Alexa_的博客

EDA与VHDL题目——八选一选择器 代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux8 IS PORT(data0,data1,data2,data3,data4,data5,data6,data7,a,b,c:IN STD_LOGIC; q:OUT STD_LOGIC); END mux8; ARCHITECTURE concunt OF mux8 IS SIGNAL sel:STD_LOGIC_VECTOR(2

EDA与VHDL题目——数字钟 代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock is port ( clk : in std_logic; reset : in std_logic; reset2 : in std_logic; xianshi : out std_logic_vector(7 downto 0)

EDA与VHDL题目——七人表决器 代码 LIBRARY IEEE; --七人表决器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY VOTE IS PORT(a,b,c,d,e,f,g:IN STD_LOGIC; -- 七输入 o:OUT STD_LOGIC); -- 一输出 END ENTITY VOTE; ARCHITECTURE VT OF VOTE IS

EDA与VHDL题目——流水灯 代码 library ieee; use ieee.std_logic_1164.all; entity runninglight is port(clk,reset:in std_logic; output:out std_logic_vector(7 downto 0)); end runninglight; architecture behave of runninglight is begin signal clk1:std_logic_vector(1 d

EDA与VHDL——模60计数器 代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt60 is port(clk,clr,ena:in std_logic; cnt10,cnt6:out std_logic_vector(3 downto 0); carry_out:out std_logic; led10:out std_logic_vect

EDA与VHDL题目——38译码器 代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; --调用库函数 ENTITY trans38 IS --结构体 PORT(A,B,C:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END trans38; ARCHITECTURE dec_behave OF trans38 IS SIGNAL sel:STD_LOGIC_VECTOR(