RISC-V Debug协议解读

此文对RISC-V Debug协议做一个简单的介绍，具体的内容，大家可以查看协议本身内容。
https://github.com/riscv/riscv-debug-spec/blob/master/riscv-debug-stable.pdf

介绍是按目录结构进行的。

1 Introduction

1. All hart registers (including CSRs) can be read/written.
2. Memory can be accessed either from the hart’s point of view, through the system bus directly, or both.
3. RV32, RV64, and future RV128 are all supported.
4. Any hart in the hardware platform can be independently debugged.
5. A debugger can discover almost everything it needs to know itself, without user configuration.
6. Each hart can be debugged from the very first instruction executed.
7. A RISC-V hart can be halted when a software breakpoint instruction is executed.
8. Hardware single-step can execute one instruction at a time.
9. Debug functionality is independent of the debug transport used.
10. The debugger does not need to know anything about the microarchitecture of the harts it is debugging.
11. Arbitrary subsets of harts can be halted and resumed simultaneously. (Optional)
12. Arbitrary instructions can be executed on a halted hart. That means no new debug functionality is needed when a core has additional or custom instructions or state, as long as there exist programs that can move that state into GPRs. (Optional)
13. Registers can be accessed without halting. (Optional)
14. A running hart can be directed to execute a short sequence of instructions, with little overhead. (Optional)
15. A system bus master allows memory access without involving any hart. (Optional)
16. A RISC-V hart can be halted when a trigger matches the PC, read/write address/data, or an instruction opcode. (Optional)
17. Harts can be grouped, and harts in the same group will all halt when any of them halts. These groups can also react to or notify external triggers. (Optional)

RISC-V Debug协议主要支持的特性就上面17点，有些是必须实现的，有些事可选的。

2 System Overview

系统总体框架：

重要的内容有：

1. The user interacts with the Debug Host (e.g. laptop), which is running a debugger (e.g. gdb). (软件层面)
2. The debugger communicates with a Debug Translator (e.g. OpenOCD, which may include a hardware driver) to communicate with Debug Transport Hardware (e.g. Olimex USB-JTAG adapter). (OpenOCD为软件，Olimex USB-JTAG adapter为硬件驱动)
3. The Debug Transport Hardware connects the Debug Host to the Platform’s Debug Transport Module (DTM). (硬件底层接收模块，例如JTAG信号的接收和处理)
4. The DTM provides access to one or more Debug Modules (DMs) using the Debug Module Interface (DMI). (接口，例如JTAG2TileLink，JTAG2AHB，一边是DTM的硬件接口，接收host的信号，一边是驱动DM模块的总线接口，驱动DM模块的总线接口由系统自行决定，可以是ABH、AXI4、TileLink或者其他简单的接口)

3 Debug Module (DM), non-ISA