Rocket-chip-Dcache Flush & Discard

本文介绍的是rocket-chip dcache flush和dachehe discard功能。

功能的说明可以参考文档《SiFive E76 Core Complex Manual 21G1.01.00》

CFLUSH.D.L1

• Implemented as state machine in L1 data cache, for cores with data caches.
• Only available in M-mode.
• When rs1 = x0, CFLUSH.D.L1 writes back and invalidates all lines in the L1 data cache.
• When rs1 != x0, CFLUSH.D.L1 writes back and invalidates the L1 data cache line containing the virtual address in integer register rs1.
• If the effective privilege mode does not have write permissions to the address in rs1, then a store access or store page-fault exception is raised.
• If the address in rs1 is in an uncacheable region with write permissions, the instruction has no effect but raises no exceptions.
• Note that if the PMP scheme write-protects only part of a cache line, then using a value for rs1 in the write-protected region will cause an exception, whereas using a value for rs1 in the write-permitted region will write back the entire cache line.

CDISCARD.D.L1

• Implemented as state machine in L1 data cache, for cores with data caches.
• Only available in M-mode.
• Opcode 0xFC200073: with optional rs1 field in bits [19:15].
• When rs1 = x0, CDISCARD.D.L1 invalidates, but does not write back, all lines in the L1 data cache. Dirty data within the cache is lost.
• When rs1 ≠ x0, CDISCARD.D.L1 invalidates, but does not write back, the L1 data cache line containing the virtual address in integer register rs1. Dirty data within the cache line is lost.
• If the effective privilege mode does not have write permissions to the address in rs1, then a store access or store page-fault exception is raised.
• If the address in rs1 is in an uncacheable region with write permissions, the instruction has no effect but raises no exceptions.
• Note that if the PMP scheme write-protects only part of a cache line, then using a value for rs1 in the write-protected region will cause an exception, whereas using a value for rs1 in the write-permitted region will invalidate and discard the entire cache line.

L1Dcache.h头文件的内容。

#include <stdint.h>

#define STR1(x) #x
#ifndef STR
#define STR(x) STR1(x)
#endif

#define CFLUSH_D_L1_REG(rs1)	\
    0xFC000073	     |		    \
    (rs1 << (7+5+3)) |          \

#define CFLUSH_D_L1_ALL()	\
    0xFC000073	     |		\

#define FLUSH_D_ALL()	\
{			\
    asm volatile (".word " STR(CFLUSH_D_L1_ALL()) "\n\t" ::: "memory"); \
}			\

//Stanard macro that passes rs1 via registers
#define FLUSH_D_REG(rs1) CFLUSH_D_L1_INST(rs1,13)

//rs1 is data
//rs_1 si the register number to use
#define CFLUSH_D_L1_INST(rs1, rs1_n) \
{				     \
    register uint32_t rs1_ asm("x" # rs1_n) = (uint32_t) rs1; \
    asm volatile (".word " STR(CFLUSH_D_L1_REG(rs1_n)) "\n\t" :: [_rs1] "r" (rs1_) : "memory"); \
}                                    \

#define CDISCARD_D_L1_REG(rs1)	\
    0xFC200073	     |		    \
    (rs1 << (7+5+3)) |          \

#define CDISCARD_D_L1_ALL()	\
    0xFC200073	     |		\

#define DISCARD_D_ALL()	\
{			\
    asm volatile (".word " STR(CDISCARD_D_L1_ALL()) "\n\t" ::: "memory"); \
}			\

//Stanard macro that passes rs1 via registers
#define DISCARD_D_REG(rs1) CDISCARD_D_L1_INST(rs1,13)

//rs1 is data
//rs_1 si the register number to use
#define CDISCARD_D_L1_INST(rs1, rs1_n) \
{				     \
    register uint32_t rs1_ asm("x" # rs1_n) = (uint32_t) rs1; \
    asm volatile (".word " STR(CDISCARD_D_L1_REG(rs1_n)) "\n\t" :: [_rs1] "r" (rs1_) : "memory"); \
}  

测试代码。

#include "encoding.h"
#include "L1Dcache.h"

#define U32 *(volatile unsigned int *)
#define DEBUG_SIG   0x70000000
#def