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RSS订阅[软件开发辅助工具].Visual.Build.Professional.v7.2.1.2-iNViSiBLE.zip
[软件开发辅助工具].Visual.Build.Professional.v7.2.1.2-iNViSiBLE
2011-03-30
mc8051_cyclone_nios_designflow.pdf
Implementing the MC8051 IP Core On A Cyclone Nios Board
First of all it is necessary to exchange the simulation models of all the memory blocks with real memory that can be found inside the target FPGA. It is also recommended to implement a PLL to get a clock signal with a lower frequency than that of the on-board oscillator. The VHDL code for these entities is generated by the backend tool, i.e. Quartus II 4.0 for Altera FPGAs
2020-06-07
mc8051_boot.zip
mc8051_bootLoader 软核8051的BootLoader Change history:
- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.
- Corrected problem with duplex operation in file
mc8051_siu_rtl.vhd
2020-06-07
mc8051_overview.pdf
MC8051 IP Core
Key Features
- Fully synchronous design
- Technology independent, clear structured, well commented VHDL source code
- Easily expandable by adapting/changing VHDL source code
- Parametrizeable design by simply changing VHDL constants
- User selectable number (N) of timers/counters and serial interface units
- Active timer/counter and serial interface units selected by additional special function register
- Instruction set compatible to the industry standard 8051 microcontroller
- Up to 10 times faster due to completely new architecture
- Optional implementation of the multiply command (MUL) using a parallel multiplier
- Optional implementation of the divide command (DIV) using a parallel divider
- Optional implementation of the decimal adjustment command (DA)
- No multiplexed I/O ports
- 256 bytes internal RAM
- Up to 64 kbyte ROM, up to 64 kbyte RAM
- Source code available free of charge under the GNU LGPL license
2020-06-07
mc8051_design_v1.6.zip
8051软核源代码
This is version 1.6 of the MC8051 IP core.
Changes:
- In certain interrupt situations the stack pointer still
has been erroneously set in control_mem_rtl.vhd, revision
1.10 and below. This has been corrected again in revision
1.11 of this file.
- The Serial Unit did not handle receives with only one
stop bit correctly in Mode1 in file mc8051_siu_rtl.vhd,
revision 1.9 and below. This has been corrected with
revision 1.10 of this file.
- The CJNE opcode did not clear the carry flag when it
should in file control_fsm_rtl.vhd, revision 1.9 and
below. This has been corrected with revision 1.10 of this
file.
2020-06-07
mc8051_user_guide.pdf
MC8051 IP Core
Synthesizable VHDL Microcontroller IP-Core User Guide
2020-06-07
mc8051_bootstrap_ug.pdf
8051 IP核 Bootstrap Demo Design User Guide 很好的资料
General Description
The following program allows the MC8051 microcontroller to load most of its code into a part of the external data memory (XRAM) over a serial link after power up. This program can be then executed out of the program memory (PRAM) for normal operation.
Any static low level routines that are unlikely to change over time can be fixed into the permanent program memory (ROM) along with the bootstrap loader which is used to load the main routine which calls the static parts of the program into the PRAM.
In the following, the memory map of the reference design is listed.
2020-06-07
B50610-DS07-RDS(博通千兆以太网手册) - 副本.pdf
B50610C1KMLG datasheet 10/100/1000BASE-T Gigabit Ethernet Transceiver
The Broadcom® B50610 is a triple-speed 1000BASE-T/ 100BASE-TX/10BASE-T Gigabit Ethernet (GbE) transceiver integrated into a single monolithic CMOS chip. The device performs all physical-layer functions for 1000BASE-T, 100BASE-TX, and 10BASE-T Ethernet on standard category 5 UTP cable. 10BASE-T can also run on standard category 3, 4, and 5 UTP. The B50610 is a highly integrated solution combining digital adaptive equalizers, ADCs, phase-locked loops, line drivers, encoders, decoders, echo cancellers, crosstalk cancellers, and all required support circuitry. Based on Broadcom’s proven Digital Signal Processor technology, the B50610 is designed to be fully compliant with RGMII, allowing compatibility with industry-standard Ethernet MACs and switch controllers.
2020-05-13
Recent Research in Control Engineering and Decision Making_2019.pdf
Recent Research in Control Engineering and Decision Making_2019， Springer出版的
2019-05-15
Nonlinear and Adaptive Control Systems：（非线性和自适应控制系统）
Nonlinear and Adaptive Control Systems：（非线性和自适应控制系统）
2019-04-06
Nonlinear and Adaptive ControlNCN42001(英文)
Nonlinear and Adaptive ControlNCN42001(英文)Nonlinear and Adaptive ControlNCN42001(英文)
2019-04-06
Nonlinear and Adaptive Control Design
Nonlinear and Adaptive Control Design 电子书 Nonlinear and Adaptive Control Design 电子书
2019-04-06
Software_Defined_Radio_using_MATLAB_Simulink_and_the_RTL-SDR.pdf
Software_Defined_Radio_using_MATLAB_Simulink_and_the_RTL-SDR.pdf,已去除文件保护，可编辑
2018-12-26
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