习题笔记 HDLBits Count clock

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该文描述了一个基于BCD码的12小时制时钟计数器设计，包括秒、分、小时和AM/PM指示器。计数器在每个秒脉冲时更新，并在达到特定状态时进行进位。重置信号具有最高优先级，可在任何状态下触发，将时钟重置为12:00AM。设计中使用了多个子模块，如秒、分的个位和十位计数器，以及小时计数器和AM/PM切换逻辑。

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    wire enable_s_10;
    wire enable_s_6;
    wire enable_m_10;
    wire enable_m_6;
    wire enable_h_12_10;
    wire enable_am_pm;

    assign enable_s_10 = ena;
    assign enable_s_6 = (ena & ss[3:0]==4'd9) ;
    assign enable_m_10 = (enable_s_6 & ss[7:4]==4'd5);  //前一位的enable信号已经包含了ena=1，所以直接用前一数位的enable信号与前一数位的输出作进位条件
    assign enable_m_6 = (enable_m_10 & mm[3:0]==4'd9);
    assign enable_h_12_10 = (enable_m_6 & mm[7:4]==4'd5);
    assign enable_am_pm = (enable_h_12_10 & hh[7:0]=={4'd1,4'd1});  //题干中为：a.m.12:00:00经过1、2、3...到a.m. 11:59:59 后变为p.m.12:00:00 到p.m. 11:59:59
                                                                    //小时为11，且分，秒各个数位都要进位时，a.m.p.m翻转

    //调用各个计数器
    BCD_10_s_m ss_10 (clk,reset,enable_s_10,ss[3:0]);
    BCD_6 ss_6 (clk,reset,enable_s_6,ss[7:4]);
    BCD_10_s_m mm_10 (clk,reset,enable_m_10,mm[3:0]);
    BCD_6 mm_6 (clk,reset,enable_m_6,mm[7:4]);
    BCD_12_h hh_12 (clk,reset,enable_h_12_10,hh[7:0]);
    am_pm am_pm (clk,reset,enable_am_pm,pm);

endmodule


//秒、分个位的十进制计数器
module BCD_10_s_m (
    input clk,
    input reset,
    input enable,
    output [3:0]q
);
    
    always @(posedge clk)
        begin
            if (reset)
                q <= 4'd0;
            else if (enable)
                q <= (q==4'd9 ? 4'd0: (q+4'b1));
        end
endmodule
 
//秒、分十位的六进制计数器
module BCD_6 (
    input clk,
    input reset,
    input enable,
    output [3:0]q
);
    
    always @(posedge clk)
        begin
            if (reset)
                q <= 4'd0;
            else if (enable)
                q <= (q==4'd5 ? 4'd0: (q+4'b1));
        end
endmodule

//小时的两个数位的十二进制计数器                    
module BCD_12_h (
    input clk,
    input reset,
    input enable,
    output [7:0]q
);
    always @(posedge clk)
        begin
            if (reset)
                q <= {4'd1,4'd2};  //reset时，小时为12
            else if (enable)
                begin
                    if (q[7:4]==4'd0)
                    begin
                        q[7:4] <= (q[3:0]==4'd9 ? 4'd1 : 4'd0);
                        q[3:0] <= (q[3:0]==4'd9 ? 4'd0 : (q[3:0]+4'd1));
                    end
                else if (q[7:4]==4'd1)
                    begin
                        q[7:4] <= (q[3:0]==4'd2 ? 4'd0 : 4'd1);
                        q[3:0] <= (q[3:0]==4'd2 ? 4'd1 :(q[3:0]+4'd1));
                    end
                end

        end
endmodule                    

//a.m. p.m. 
module am_pm (
    input clk,
    input reset,
    input enable,
    output am_pm
);
    always @(posedge clk)
           begin
              if (reset)
                am_pm <= 1'b0;
              else if (enable)
                am_pm <= ~am_pm;
           end

endmodule