/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* iav_ioctl.h
*
* History:
* 2021/02/18 - [Zhaoyang Chen] Created file
*
* Copyright (c) 2021 Ambarella International LP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef __IAV_IOCTL_H__
#define __IAV_IOCTL_H__
/*! @file iav_ioctl.h
* @brief This file defines IAV driver ioctl api.
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <basetypes.h>
#include <linux/ioctl.h>
#include <board_config.h>
#include <iav_common.h>
#include <iav_vin_ioctl.h>
#include <iav_vout_ioctl.h>
#include <ambas_imgproc_arch.h>
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
/*! @def IAV_API_VER_MAJOR
* @brief define IAV API Major Version.
*/
#define IAV_API_VER_MAJOR (1)
/*! @def IAV_API_VER_MINOR
* @brief define IAV API Minor Version.
*/
#define IAV_API_VER_MINOR (22)
/*! @def IAV_API_VER_PATCH
* @brief define IAV API Patch Version.
*/
#define IAV_API_VER_PATCH (1)
/*! @def IAV_API_VER_MOD_TIME
* @brief define IAV API Modification/Update Time.
*/
#define IAV_API_VER_MOD_TIME (0x20250828)
/*! @def IAV_MAX_CHANNEL_NUM
* @brief define max channel number.
*/
#ifndef CONFIG_AMBARELLA_MAX_CHANNEL_NUM
#define CONFIG_AMBARELLA_MAX_CHANNEL_NUM (1)
#endif
#ifndef IAV_MAX_CHANNEL_NUM
#define IAV_MAX_CHANNEL_NUM (16)
#endif
/*! @def IAV_HEVC_TILE_NUM
* @brief define iav hevc encode tile number.
*/
#define IAV_HEVC_TILE_NUM (5)
/*! @def IAV_MAX_PYRAMID_LAYERS
* @brief define iav max pyramid layer number.
*/
#define IAV_MAX_PYRAMID_LAYERS (7)
/*! @def IAV_MAX_PASS_NUM
* @brief define iav max pass number for each channel.
*/
#define IAV_MAX_PASS_NUM (2)
/*! @def IAV_MAX_FUSION_CHAN_NUM
* @brief define iav max fusion channel number.
*/
#define IAV_MAX_FUSION_CHAN_NUM (2)
/*! @def IAV_MAX_REAL_VIN_NUM
* @brief define real vin instance number.
*/
#if defined(AMBA_SOC_N1)
#define IAV_MAX_REAL_VIN_NUM (24)
#elif defined(AMBA_SOC_CV75)
#define IAV_MAX_REAL_VIN_NUM (10)
#else
#define IAV_MAX_REAL_VIN_NUM (14)
#endif
/*! @def IAV_MAX_VIRT_VIN_NUM
* @brief define virtual vin instance number.
*/
#if defined(AMBA_SOC_N1)
#define IAV_MAX_VIRT_VIN_NUM (8)
#elif defined(AMBA_SOC_N1_655)
#define IAV_MAX_VIRT_VIN_NUM (16)
#else
#define IAV_MAX_VIRT_VIN_NUM (12)
#endif
/*! @def IAV_VIN_ROI_WIN_ALIGN
* @brief align vin roi window to 2.
*/
#define IAV_VIN_ROI_WIN_ALIGN (2)
/*! @def VIN_INSTANCES
* @brief define vin instance number.
*/
#define VIN_INSTANCES (IAV_MAX_REAL_VIN_NUM + IAV_MAX_VIRT_VIN_NUM)
/*! @def VIN_CONTROLLER_NUM
* @brief define vin controller number, equal to VIN_INSTANCES.
*/
#define VIN_CONTROLLER_NUM VIN_INSTANCES
/*! @def IAV_MAX_EFR_VIN_NUM
* @brief define maximum raw encode VIN number, it uses the virtual vin instance number.
*/
#define IAV_MAX_EFR_VIN_NUM (8)
/*! @def IAV_MAX_VIN_EFR_CHAN_NUM
* @brief define max channel number for a single raw encode VIN.
*/
#define IAV_MAX_VIN_EFR_CHAN_NUM (4)
/*! @def IAV_MAX_EXTRA_RAW_LINES
* @brief define iav max extra raw cap lines.
*/
#define IAV_MAX_EXTRA_RAW_LINES (8)
/*! @def IAV_MAX_RAWSEQ_NUM
* @brief define max raw sequence numbers to get. It's used for some special
* use case, such as ToF sensor which need to read out continuous 8 (or 12)
* frames RAW data in one shot.
*/
#define IAV_MAX_RAWSEQ_NUM (12)
/*! @def IAV_MAX_MOTION_TYPE_NUM
* @brief define max motion data type number, two types of motion A and motion B
* are supported.
*/
#define IAV_MAX_MOTION_TYPE_NUM (2)
/*! @def IAV_ENC_H26X_MIN_WIDTH_IN_CODEC
* @brief define minimum H26X encoding width supported by Codec. For streams with
* smaller width, will add horizontal cropping at VUI info.
*/
#define IAV_ENC_H26X_MIN_WIDTH_IN_CODEC (256)
/*! @def IAV_ENC_H26X_MIN_HEIGHT_IN_CODEC
* @brief define minimum H26X encoding height supported by Codec. For streams with
* smaller height, will add vertical cropping at VUI info.
*/
#define IAV_ENC_H26X_MIN_HEIGHT_IN_CODEC (256)
/*! @def LPDDR4_ALIGN
* @brief define lpddr4 align value.
*/
#define LPDDR4_ALIGN (64)
#ifndef IAV_DSP_BUF_PITCH_ALIGN
#if defined(AMBA_SOC_CV5) || defined(AMBA_SOC_CV52)
#define IAV_DSP_BUF_PITCH_ALIGN (64)
#else
/* For CV72 and later, align buffer pitch size to 128B. */
#define IAV_DSP_BUF_PITCH_ALIGN (128)
#endif
#endif
/*! @def IAV_MIN_PMRD_EXT_MEM_BUF_NUM
* @brief define pyramid ext mem buf min limit.
*/
#define IAV_MIN_PMRD_EXT_MEM_BUF_NUM (4)
/*! @def IAV_MAX_PMRD_EXT_MEM_BUF_NUM
* @brief define pyramid ext mem buf max limit.
*/
#define IAV_MAX_PMRD_EXT_MEM_BUF_NUM (100)
/*! @def IAV_MAX_ENCODE_FRAMERATE_UPSAMPLING_RATIO
* @brief define encode framerate upsamling maximum ratio.
*/
#define IAV_MAX_ENCODE_FRAMERATE_UPSAMPLING_RATIO (1)
/*! @def IAV_MAX_IRQ_SKIP_CNT
* @brief define max DSP IRQ skip count limit.
*/
#define IAV_MAX_IRQ_SKIP_CNT (120)
/*! @def IAV_HP_FPS_FACTOR
* @brief define high precision fps factor.
*/
#define IAV_HP_FPS_FACTOR (1000)
/*! @def IAV_HP_FPS_MAX
* @brief define maximum high precision fps.
*/
#define IAV_HP_FPS_MAX (960000) /*!< 960fps */
/*! @def IAV_Q9_FPS_MAX
* @brief define maximum fps in q9 format.
*/
#define IAV_Q9_FPS_MAX (1066666) /*!< 480fps */
/*! @def IAV_HP_FPS_MIN
* @brief define minimum high precision fps.
*/
#define IAV_HP_FPS_MIN (500) /*!< 0.5fps */
/*! @def IAV_Q9_FPS_MIN
* @brief define minimum fps in q9 format.
*/
#define IAV_Q9_FPS_MIN (1024000000) /*!< 0.5fps */
/*! @def UNIQUE_ID_SIZE
* @brief define unique ID size.
*/
#define UNIQUE_ID_SIZE (32)
/*! @def IAV_EXTRA_ISO_CFG_MAX
* @brief define the max extra iso_cfg buffer number.
*/
#define IAV_EXTRA_ISO_CFG_MAX (16)
/*! @def IAV_DSP_AUDIT_INT_NUM
* @brief define the dsp auditable interrupt number.
*/
#define IAV_DSP_AUDIT_INT_NUM (5)
/*! @def IAV_ENC_H26X_WIDTH_ALIGN
* @brief define H264 and H265 encoding width align requirement.
*/
#define IAV_ENC_H26X_WIDTH_ALIGN (4)
/*! @def IAV_ENC_H26X_HEIGHT_ALIGN
* @brief define H264 and H265 encoding height align requirement.
*/
#define IAV_ENC_H26X_HEIGHT_ALIGN (4)
/*! @def IAV_ENC_MJPEG_WIDTH_ALIGN
* @brief define MJPEG encoding width align requirement.
*/
#define IAV_ENC_MJPEG_WIDTH_ALIGN (4)
/*! @def IAV_ENC_MJPEG_HEIGHT_ALIGN
* @brief define MJPEG encoding height align requirement.
*/
#define IAV_ENC_MJPEG_HEIGHT_ALIGN (4)
/*! @def IAV_ENC_X_OFFSET_ALIGN
* @brief define encoding x-offset align requirement.
*/
#define IAV_ENC_X_OFFSET_ALIGN (2)
/*! @def IAV_ENC_Y_OFFSET_ALIGN
* @brief define encoding y-offset align requirement.
*/
#define IAV_ENC_Y_OFFSET_ALIGN (4)
/*! @def IAV_MAX_IDSP_VER_SLICE_NUM
* @brief define the max IDSP frame vertical slice number.
*/
#define IAV_MAX_IDSP_VER_SLICE_NUM (2)
/*! @def IAV_CANVAS_WIDTH_ALIGN
* @brief define canvas width align requirement.
*/
#define IAV_CANVAS_WIDTH_ALIGN (2)
/*! @def IAV_CANVAS_HEIGHT_ALIGN
* @brief define canvas height align requirement.
*/
#define IAV_CANVAS_HEIGHT_ALIGN (2)
/*! @def IAV_CANVAS_WIDTH_MAX
* @brief define canvas max width.
*/
#define IAV_CANVAS_WIDTH_MAX (15360)
/*! @def IAV_CANVAS_HEIGHT_MAX
* @brief define canvas max height.
*/
#define IAV_CANVAS_HEIGHT_MAX (8640)
/*! @enum dsp_mode
* @brief DSP mode enum to list dsp mode state.
*/
enum dsp_mode {
DSP_CURRENT_MODE = 0xFF, /*!< 0xFF */
DSP_NORMAL_ISO_MODE = 0x0, /*!< 0x0 */
DSP_MULTI_REGION_WARP_MODE = 0x1, /*!< 0x1 */
DSP_HORIZON_KEEPING_MODE = 0x3, /*!< 0x3 */
DSP_MULTI_OUTPUT_FUSION_MODE = 0x4, /*!< 0x4 */
DSP_HDR_LINE_INTERLEAVED_MODE = 0x5, /*!< 0x5 */
DSP_ADVANCED_ISO_MODE = 0x5, /*!< alias of DSP_HDR_LINE_INTERLEAVED_MODE */
DSP_IMG_PIPE_ONLY_MODE = 0x8, /*!< 0x8 */
DSP_AISP_MODE = 0x9, /*!< 0x9 */
DSP_MULTI_REGION_DPTZ_MODE = 0xA, /*!< 0xA */
DSP_ENCODE_MODE_TOTAL_NUM = 0xB, /*!< 0xB */
DSP_VIN_ONLY_MODE = 0x7F, /*!< 0x7F */
DSP_ENCODE_MODE_AUTOMATIC = 0x80, /*!< 0x80 */
DSP_ENCODE_MODE_FIRST = DSP_NORMAL_ISO_MODE, /*!< DSP_NORMAL_ISO_MODE */
DSP_ENCODE_MODE_LAST = DSP_ENCODE_MODE_TOTAL_NUM, /*!< DSP_ENCODE_MODE_TOTAL_NUM */
};
/*! @enum hevc_perf_mode
* @brief HEVC performance mode enumeration.
*/
enum hevc_perf_mode {
IAV_HEVC_PERF_MODE_DEFAULT = 0,
IAV_HEVC_PERF_MODE_GOOD_QUALITY = 1,
IAV_HEVC_PERF_MODE_EXCELLENT_QUALITY = 2,
IAV_HEVC_PERF_MODE_NUM = 3,
IAV_HEVC_PERF_MODE_FIRST = IAV_HEVC_PERF_MODE_DEFAULT,
IAV_HEVC_PERF_MODE_LAST = IAV_HEVC_PERF_MODE_NUM,
};
/*! @enum iav_chip_id
* @brief iav chip id enumeration.
*/
enum iav_chip_id {
IAV_CHIP_ID_UNKNOWN = -1,
IAV_CHIP_ID_UNAVAILABLE = -2,
/* CV5 */
IAV_CHIP_ID_CV5_99 = 0x00, /*!< 0x00 */
IAV_CHIP_ID_CV5_88 = 0x01, /*!< 0x01 */
IAV_CHIP_ID_CV5_66 = 0x02, /*!< 0x02 */
IAV_CHIP_ID_CV5_LAST = 0x03, /*!< 0x03 */
IAV_CHIP_ID_CV5_FIRST = IAV_CHIP_ID_CV5_99, /*!< IAV_CHIP_ID_CV5_99 */
IAV_CHIP_ID_CV5_NUM = IAV_CHIP_ID_CV5_LAST - IAV_CHIP_ID_CV5_FIRST, /*!< IAV_CHIP_ID_CV5_LAST - IAV_CHIP_ID_CV5_FIRST */
/* CV52 */
IAV_CHIP_ID_CV52_99 = 0x00, /*!< 0x00 */
IAV_CHIP_ID_CV52_66 = 0x01, /*!< 0x01 */
IAV_CHIP_ID_CV52_33 = 0x02, /*!< 0x02 */
IAV_CHIP_ID_CV52_LAST = 0x03, /*!< 0x03 */
IAV_CHIP_ID_CV52_FIRST = IAV_CHIP_ID_CV52_99, /*!< IAV_CHIP_ID_CV52_99 */
IAV_CHIP_ID_CV52_NUM = IAV_CHIP_ID_CV52_LAST - IAV_CHIP_ID_CV52_FIRST, /*!< IAV_CHIP_ID_CV52_LAST - IAV_CHIP_ID_CV52_FIRST */
/* CV72 */
IAV_CHIP_ID_CV72_99 = 0x00, /*!< 0x00 */
IAV_CHIP_ID_CV72_88 = 0x01, /*!< 0x01 */
IAV_CHIP_ID_CV72_88IQ = 0x02, /*!< 0x02 */
IAV_CHIP_ID_CV72_66 = 0x03, /*!< 0x03 */
IAV_CHIP_ID_CV72_66IQ = 0x04, /*!< 0x04 */
IAV_CHIP_ID_CV72_33 = 0x05, /*!< 0x05 */
IAV_CHIP_ID_CV72_LAST = 0x06, /*!< 0x06 */
IAV_CHIP_ID_CV72_FIRST = IAV_CHIP_ID_CV72_99, /*!< IAV_CHIP_ID_CV72_99 */
IAV_CHIP_ID_CV72_NUM = IAV_CHIP_ID_CV72_LAST - IAV_CHIP_ID_CV72_FIRST, /*!< IAV_CHIP_ID_CV72_LAST - IAV_CHIP_ID_CV72_FIRST */
/* CV72 AUTO */
IAV_CHIP_ID_CV72AX_86 = 0x20, /*!< 0x00 */
IAV_CHIP_ID_CV72AX_76 = 0x21, /*!< 0x21 */
IAV_CHIP_ID_CV72AX_56 = 0x22, /*!< 0x22 */
IAV_CHIP_ID_CV72AQ_86 = 0x23, /*!< 0x23 */
IAV_CHIP_ID_CV72AQ_76 = 0x24, /*!< 0x24 */
IAV_CHIP_ID_CV72AQ_56 = 0x25, /*!< 0x25 */
IAV_CHIP_ID_CV72AUTO_LAST = 0x26, /*!< 0x26 */
IAV_CHIP_ID_CV72AUTO_FIRST = IAV_CHIP_ID_CV72AX_86, /*!< IAV_CHIP_ID_CV72AX_86 */
IAV_CHIP_ID_CV72AUTO_NUM = IAV_CHIP_ID_CV72AUTO_LAST - IAV_CHIP_ID_CV72AUTO_FIRST, /*!< IAV_CHIP_ID_CV72AUTO_LAST - IAV_CHIP_ID_CV72AUTO_FIRST */
/* N1 */
IAV_CHIP_ID_N1_99 = 0x00, /*!< 0x00 */
IAV_CHIP_ID_N1_LAST = 0x01, /*!< 0x01 */
IAV_CHIP_ID_N1_FIRST = IAV_CHIP_ID_N1_99, /*!< IAV_CHIP_ID_N1_99 */
IAV_CHIP_ID_N1_NUM = IAV_CHIP_ID_N1_LAST - IAV_CHIP_ID_N1_FIRST, /*!< IAV_CHIP_ID_N1_LAST - IAV_CHIP_ID_N1_FIRST */
/* N1 655 */
IAV_CHIP_ID_N1_655_99 = 0x00, /*!< 0x00 */
IAV_CHIP_ID_N1_655_LAST = 0x01, /*!< 0x01 */
IAV_CHIP_ID_N1_655_FIRST = IAV_CHIP_ID_N1_655_99, /*!< IAV_CHIP_ID_N1_655_99 */
IAV_CHIP_ID_N1_655_NUM = IAV_CHIP_ID_N1_655_LAST - IAV_CHIP_ID_N1_655_FIRST, /*!< IAV_CHIP_ID_N1_655_LAST - IAV_CHIP_ID_N1_655_FIRST */
/* CV75 */
IAV_CHIP_ID_CV75_99 = 0x00, /*!< 0x00 */
IAV_CHIP_ID_CV75_98 = 0x01, /*!< 0x01 */
IAV_CHIP_ID_CV75_88 = 0x02, /*!< 0x02 */
IAV_CHIP_ID_CV75_66 = 0x03, /*!< 0x03 */
IAV_CHIP_ID_CV75_33 = 0x04, /*!< 0x04 */
IAV_CHIP_ID_CV75_99M = 0x05, /*!< 0x05 */
IAV_CHIP_ID_CV75_88M = 0x06, /*!< 0x06 */
IAV_CHIP_ID_CV75_55M = 0x07, /*!< 0x07 */
IAV_CHIP_ID_CV75_33M = 0x08, /*!< 0x08 */
IAV_CHIP_ID_CV75_33EX = 0x09, /*!< 0x09 */
IAV_CHIP_ID_CV75_68EX = 0x0a, /*!< 0x0a */
IAV_CHIP_ID_CV75_LAST = 0x0b, /*!< 0x0b */
IAV_CHIP_ID_CV75_FIRST = IAV_CHIP_ID_CV75_99, /*!< IAV_CHIP_ID_CV75_99 */
IAV_CHIP_ID_CV75M_LAST = IAV_CHIP_ID_CV75_LAST, /*!< IAV_CHIP_ID_CV75_LAST */
IAV_CHIP_ID_CV75M_FIRST = IAV_CHIP_ID_CV75_99M, /*!< IAV_CHIP_ID_CV75_99M */
IAV_CHIP_ID_CV75_NUM = IAV_CHIP_ID_CV75_LAST - IAV_CHIP_ID_CV75_FIRST, /*!< IAV_CHIP_ID_CV75_LAST - IAV_CHIP_ID_CV75_FIRST */
/* CV75 AUTO */
IAV_CHIP_ID_CV75AX_86 = 0x20, /*!< 0x20 */
IAV_CHIP_ID_CV75AX_76 = 0x21, /*!< 0x21 */
IAV_CHIP_ID_CV75AX_56 = 0x22, /*!< 0x22 */
IAV_CHIP_ID_CV75AQ_86 = 0x23, /*!< 0x23 */
IAV_CHIP_ID_CV75AQ_76 = 0x24, /*!< 0x24 */
IAV_CHIP_ID_CV75A_96 = 0x25, /*!< 0x25 */
IAV_CHIP_ID_CV75A_76 = 0x26, /*!< 0x26 */
IAV_CHIP_ID_CV75A_56 = 0x27, /*!< 0x27 */
IAV_CHIP_ID_CV75AUTO_LAST = 0x28, /*!< 0x28 */
IAV_CHIP_ID_CV75AUTO_FIRST = IAV_CHIP_ID_CV75AX_86, /*!< IAV_CHIP_ID_CV75AX_86 */
IAV_CHIP_ID_CV75AUTO_NUM = IAV_CHIP_ID_CV75AUTO_LAST - IAV_CHIP_ID_CV75AUTO_FIRST, /*!< IAV_CHIP_ID_CV75AUTO_LAST - IAV_CHIP_ID_CV75AUTO_FIRST */
};
/*! @enum iav_hp_fps
* @brief iav high precision fps enumeration.
*/
enum iav_hp_fps {
IAV_HP_FPS_AUTO = 0, /*!< 0 */
IAV_HP_FPS_3_125 = 3125, /*!< 3125 = 3.125 * 1000 */
IAV_HP_FPS_3_75 = 3750, /*!< 3750 = 3.75 * 1000 */
IAV_HP_FPS_6_25 = 6250, /*!< 6250 = 6.25 * 1000 */
IAV_HP_FPS_7_5 = 7500, /*!< 7500 = 7.5 * 1000 */
IAV_HP_FPS_12_5 = 12500, /*!< 12500 = 12.5 * 1000 */
IAV_HP_FPS_15 = 15000, /*!< 15000 = 15 * 1000 */
IAV_HP_FPS_23_976 = 23976, /*!< 23976 = 23.976 * 1000 */
IAV_HP_FPS_24 = 24000, /*!< 24000 = 24 * 1000 */
IAV_HP_FPS_25 = 25000, /*!< 25000 = 25 * 1000 */
IAV_HP_FPS_29_97 = 29970, /*!< 29970 = 29.97 * 1000 */
IAV_HP_FPS_30 = 30000, /*!< 30000 = 30 * 1000 */
IAV_HP_FPS_50 = 50000, /*!< 50000 = 50 * 1000 */
IAV_HP_FPS_59_94 = 59940, /*!< 59940 = 59.94 * 1000 */
IAV_HP_FPS_60 = 60000, /*!< 60000 = 60 * 1000 */
IAV_HP_FPS_120 = 120000, /*!< 120000 = 120 * 1000 */
};
/*! @enum iav_aisp_type
* @brief iav aisp type enumeration.
*/
enum iav_aisp_type {
IAV_AISP_TYPE_DEFAULT = 0, /*!< Ambarella AISP */
IAV_AISP_TYPE_CUSTOM = 1, /*!< Custom AISP */
IAV_AISP_TYPE_NUM,
};
/*! @enum iav_aisp_map_type
* @brief iav AISP interface map type enumeration.
*/
enum iav_aisp_map_type {
IAV_AISP_MAP_TYPE_PORT = 0,
IAV_AISP_MAP_TYPE_POKE = 1,
IAV_AISP_MAP_TYPE_NUM,
};
/*! @enum iav_aisp_nn_type
* @brief iav AISP net type enumeration.
*/
enum iav_aisp_nn_type {
/*
* For both 1080p and 4K NN, there is 1 MD model; and 2 C2Y models : 1 C2Y_R model,
* 1 C2Y_L model.
*
* For MD NN :
* it is same for 1080p and 4K case, just load it once.
*
* For C2Y NN :
* There are 2 tiles for 1080p case, so just need load 1 C2Y_R and 1 C2Y_L.
* However there are 4 tiles for 4K case (3 left tiles and 1 right tile).
* To save memory, APP just still load once C2Y_L NN, but prepare 3 run_dag_cmds.
* IAV_AISP_NN_TYPE_C2Y_L0, IAV_AISP_NN_TYPE_C2Y_L1, IAV_AISP_NN_TYPE_C2Y_L2
* are for different tiles with different run_dag_cmd but from the same C2Y_L NN.
*/
IAV_AISP_NN_TYPE_MD = 0,
IAV_AISP_NN_TYPE_C2Y_R = 1,
IAV_AISP_NN_TYPE_C2Y_L0 = 2,
IAV_AISP_NN_TYPE_C2Y_L1 = 3,
IAV_AISP_NN_TYPE_C2Y_L2 = 4,
IAV_AISP_NN_TYPE_TOTAL_NUM = 8,
};
/*! @enum iav_isp_nn_id
* @brief iav ISP NN net id enumeration.
*/
enum iav_isp_nn_id {
IAV_ISP_NN_MD = 0,
IAV_ISP_NN_CE = 1,
IAV_ISP_NN_C2C_L = 2,
IAV_ISP_NN_C2C_R = 3,
IAV_ISP_NN_TOTAL_MAX = 8,
};
/*! @enum iav_isp_nn_type
* @brief iav ISP NN type enumeration.
*/
enum iav_isp_nn_type {
IAV_ISP_NN_TYPE_NONE = 0,
IAV_ISP_NN_TYPE_MD = 1, /*!< True Motion */
IAV_ISP_NN_TYPE_TONE_MAPPING = 2, /*!< Vivid HDR */
IAV_ISP_NN_TYPE_MD_TONE_MAPPING = 3, /*!< Vivid HDR with True Motion */
IAV_ISP_NN_TYPE_HDR_MD = 4, /*!< HDR True Motion */
IAV_ISP_NN_TYPE_C2C = 5, /*!< AISP */
IAV_ISP_NN_TYPE_NUM = 6,
};
/*! @enum iav_isp_nn_cfg_type
* @brief iav ISP NN config enumeration.
*/
enum iav_isp_nn_cfg_type {
IAV_ISP_NN_CFG = 1,
IAV_ISP_NN_CFG_TYPE_MAX = 2,
};
/*! @enum iav_ce_format
* @brief iav ce format enumeration.
*/
enum iav_ce_format {
IAV_CE_FORMAT_4H1V = 0, /*!< width: 1/4 raw width height: full raw height. */
IAV_CE_FORMAT_2H2V = 1, /*!< width: 1/2 raw width height: 1/2 raw height. */
IAV_CE_FORMAT_4H2V = 2, /*!< width: 1/4 raw width height: 1/2 raw height. */
IAV_CE_FORMAT_4H4V = 3, /*!< width: 1/4 raw width height: 1/4 raw height. */
IAV_CE_FORMAT_NUM,
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_driver_version {
int arch; /*!< Chip arch ID */
int model; /*!< Chip model ID */
int major; /*!< Major of the device driver version */
int minor; /*!< Minor of the device driver version */
int patch; /*!< Patch of the device driver version */
u32 mod_time; /*!< Last modification time of the device driver */
char description[64]; /*!< Description of the device driver */
u32 api_version; /*!< API version */
u32 dsp_version; /*!< DSP version */
u32 iav_api_version; /*!< IAV API version */
u32 iav_api_mode_time; /*!< Last modification time of the IAV API */
};
struct iav_driver_dsp_info {
struct iav_driver_version drv_ver; /*!< Driver version information */
u32 dspid; /*!< DSP Chip ID */
};
struct iav_dsplog_setup {
int cmd; /*!< Not currently supported. */
u32 module; /*!< DSP modules map. */
u32 level; /*!< DSP log level.
Log level:
0 : Silent
1 : MINIMAL
2 : NORMAL
3 : VERBOSE
4 : DEBUG
*/
u32 mask;
u32 args[6];
};
struct iav_aisp_nn_info {
unsigned long dag_addr_phys_addr; /*!< Memory physical address where stores dag_addr.*/
unsigned long port_map_phys_addr; /*!< Memory physical address where stores port map of each interface.*/
u32 nn_id : 8; /*!< NN ID for each AISP DAG. */
u32 is_port_pos : 1; /*!< Flag to configure port pos valiation */
u32 reserved0 : 23;
u32 reserved1;
unsigned long port_pos_map_phys_addr; /*!< Memory physical address where stores port pos */
u32 reserved2[2]; /*!< Align structure size to 40 bytes */
};
struct iav_isp_nn_info {
unsigned long dag_addr_phys_addr; /*!< Memory physical address where stores dag_addr.*/
unsigned long port_map_phys_addr; /*!< Memory physical address where stores port map of each interface.*/
u32 nn_id : 8; /*!< NN ID for each ISP NN DAG. */
u32 is_port_pos : 1; /*!< Flag to configure port pos valiation */
u32 reserved0 : 23;
u32 reserved1;
unsigned long port_pos_map_phys_addr; /*!< Memory physical address where stores port pos */
};
/* img_also should prepare all Ambarella AISP cfg info in continous memory, and then feed each
* info base physical address to IAV, IAV bypass these addresses to DSP.
*/
struct iav_aisp_cfg {
u8 active_type_cnt; /*!< Active NN model type cnt for each group */
u8 max_dag_cnt; /*!< Maximum value of dag_cnt for NN model in all the group */
u8 reserved0[2];
u32 fifo_addr; /*!< AISP fifo base physical address, partition_id : 'CMD_IDSP' of cavalry memory layout */
u32 fifo_len; /*!< AISP fifo length, it should be equal to length of CMD_IDSP partition */
u16 width; /*!< AISP supported width of image */
u16 height; /*!< AISP supported height of image */
enum amba_video_hdr_mode hdr_mode; /*!< HDR mode, @sa amba_video_hdr_mode */
u32 reserved1;
struct iav_aisp_nn_info nn_info[IAV_AISP_NN_TYPE_TOTAL_NUM]; /*!< nn_info for each NN model */
u32 reserved2[42]; /* Aligned to 512B */
};
struct iav_isp_nn_cfg {
u8 chan_id; /*!< Specifies the channel ID for ISP NN set up */
u8 reserved0[3];
enum iav_isp_nn_type type; /*!< Specifies the ISP NN type */
u8 active_type_cnt; /*!< Active NN model type cnt for each group */
u8 max_dag_cnt; /*!< Maximum value of dag_cnt for NN model in all the group */
u8 reserved1[2];
u32 fifo_addr; /*!< NN fifo base physical address, partition_id : 'CMD_IDSP' of cavalry memory layout */
u32 fifo_len; /*!< NN fifo length, it should be equal to length of CMD_IDSP partition */
u32 reserved2;
struct iav_isp_nn_info nn_info[IAV_ISP_NN_TOTAL_MAX]; /*!< nn_info for each NN model */
u16 width; /*!< NN supported width of image */
u16 height; /*!< NN supported hight of image */
enum amba_video_hdr_mode hdr_mode; /*!< HDR mode, @sa amba_video_hdr_mode */
u32 reserved3[40]; /* Aligned to 256B */
};
struct iav_aisp_params {
enum iav_aisp_type type; /*!< Specify AISP type. */
union {
struct iav_aisp_cfg aisp; /*!< Amba AISP cfg. */
} arg;
};
struct iav_isp_nn_params {
enum iav_isp_nn_cfg_type cfg_type; /*!< Specify config type. */
union {
struct iav_isp_nn_cfg nn_cfg; /*!< Amba NN cfg. */
} arg;
};
struct iav_dsp_boot_params {
u32 debug_chip_id_flag : 1; /*!< Flag to config debug-chip-id */
u32 vout_osd_rescale_flag : 1; /*!< Flag to config vout_osd_rescale_disable. */
u32 vout_possible_map_flag : 1; /*!< Flag to config vout_possible_map. */
u32 hdmi_yuv420_possible_flag : 1; /*!< Flag to config hdmi_yuv420_possible. */
u32 quick_mode_switch_flag : 1; /*!< Flag to config quick_mode_switch. */
u32 reserved0 : 27;
u8 debug_chip_id; /*!< Specify debug-chip-id to do simulation, @sa iav_chip_id
It's ONLY for internal debug purpose and works ONLY on engineering chip samples. */
u8 vout_osd_rescale_disable : 1; /*!< Flag to disable VOUT OSD rescale.
Multiple VOUTs are supported only when VOUT OSD rescale is disabled. */
u8 vout_possible_map : 3; /*!< Specify possible vout map when booting stage. */
u8 hdmi_yuv420_possible : 1; /*!< Specify hdmi yuv420 mode switch possible at booting stage. */
u8 quick_mode_switch : 1; /*!< Flag to enable / disable quick mode switch between IDLE and preview. */
u8 reserved1 : 2;
u8 reserved2[2];
u32 reserved3[14]; /*!< Aligned to 64B */
};
struct vout_max_res {
u32 id; /*!< VOUT ID */
u32 osd_bit_depth; /*!< VOUT OSD max bit depth */
u32 vout_win_width; /*!< VOUT max window width */
u32 osd_win_width; /*!< VOUT OSD max window width */
u32 virtual_channel_num; /*!< VOUT max virtual channel number */
};
struct vout_max_res_params {
u32 num; /*!< VOUT number */
struct vout_max_res res[VOUT_NUM]; /*!< VOUT max resources */
};
struct iav_idle_params {
u8 poweroff_vin : 1; /*!< Flag to power off all VIN controller when DSP enter IDLE mode. */
u8 no_vout_reset : 1; /*!< Flag to disable VOUT reset when DSP enters IDLE state. */
u8 no_reset_vout_map : 3; /*!< Specify vout map if such vout will not be reset when no_vout_reset is enabled. */
u8 reserved0 : 3;
u8 reserved1[3];
struct iav_dsp_boot_params dsp_boot_params; /*!< Parameters ONLY used in DSP boot stage */
};
struct iav_preview_params {
u8 no_vout_reset : 1; /*!< Flag to disable VOUT reset when DSP enters preview state. */
u8 no_reset_vout_map : 3; /*!< Specify vout map if such vout will not be reset when no_vout_reset is enabled. */
u8 reserved0 : 4;
u8 reserved1[3];
u32 reserved2[7]; /*!< Aligned to 32B */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum iav_state {
IAV_STATE_INIT = -1, /*!< -1 */
IAV_STATE_IDLE = 0, /*!< 0 */
IAV_STATE_PREVIEW = 1, /*!< 1 */
IAV_STATE_ENCODING = 2, /*!< 2 */
IAV_STATE_STILL_CAPTURE = 3, /*!< 3 */
IAV_STATE_DECODING = 4, /*!< 4 */
IAV_STATE_TRANSCODING = 5, /*!< 5 */
IAV_STATE_DUPLEX = 6, /*!< 6 */
IAV_STATE_EXITING_PREVIEW = 7, /*!< 7 */
IAV_STATE_ACTIVATING_PREVIEW = 8, /*!< 8 */
IAV_STATE_DEBUG_DRAM_TEST = 0x80, /*!< 128 */
};
enum iav_boot_mode {
SYSTEM_NORMAL_BOOT = 0, /*!< 0 */
SYSTEM_FAST_BOOT = 1, /*!< 1 */
};
enum iav_system_query_source {
SYSTEM_PROCESS_GENERIC = 0, /*!< 0 */
SYSTEM_PROCESS_IMAGE = 1, /*!< 1 */
};
enum iav_canvas_type {
IAV_CANVAS_TYPE_OFF = 0, /*!< 0, This canvas is disabled. */
IAV_CANVAS_TYPE_ENCODE = 1, /*!< 1, This canvas type is for ENCODE only. Canvas YUV format is YUV420 only. */
IAV_CANVAS_TYPE_PREVIEW = 2, /*!< 2, This canvas type is for PREVIEW only. Canvas YUV format is YUV420 only. */
IAV_CANVAS_TYPE_ENCODE_PREVIEW = 3, /*!< 3, This canvas type is for "ENCODE + PREVIEW" simultaneously. Canvas YUV format is YUV420 only. */
IAV_CANVAS_TYPE_NUM = 4, /*!< 4, Total number of canvas type. */
};
enum iav_canvas_state {
IAV_CANVAS_STATE_UNKNOWN = 0, /*!< 0 */
IAV_CANVAS_STATE_IDLE = 1, /*!< 1 */
IAV_CANVAS_STATE_BUSY = 2, /*!< 2 */
IAV_CANVAS_STATE_ERROR = 255, /*!< 255 */
};
enum iav_canvas_src_buf_align {
IAV_CANVAS_SRC_BUF_ALIGN_64 = 0, /*!< 0 */
IAV_CANVAS_SRC_BUF_ALIGN_128 = 1, /*!< 1 */
IAV_CANVAS_SRC_BUF_ALIGN_256 = 2, /*!< 2 */
IAV_CANVAS_SRC_BUF_ALIGN_512 = 3, /*!< 3 */
IAV_CANVAS_SRC_BUF_ALIGN_TYPE_NUM = 4, /*!< 4 */
};
enum iav_efm_state {
IAV_EFM_STATE_UNKNOWN = 0, /*!< 0 */
IAV_EFM_STATE_IDLE = 1, /*!< 1 */
IAV_EFM_STATE_BUSY = 2, /*!< 2 */
IAV_EFM_STATE_ERROR = 255, /*!< 255 */
};
enum iav_stream_type {
IAV_STREAM_TYPE_NONE = 0x0, /*!< 0x0 */
IAV_STREAM_TYPE_H264 = 0x1, /*!< 0x1 */
IAV_STREAM_TYPE_MJPEG = 0x2, /*!< 0x2 */
IAV_STREAM_TYPE_H265 = 0x3, /*!< 0x3 */
IAV_STREAM_TYPE_NUM = 0x4, /*!< 0x4 */
IAV_STREAM_TYPE_INVALID = 0xFF, /*!< 0xFF */
};
enum iav_stream_state {
IAV_STREAM_STATE_IDLE = 0, /*!< 0 */
IAV_STREAM_STATE_STARTING = 1, /*!< 1 */
IAV_STREAM_STATE_ENCODING = 2, /*!< 2 */
IAV_STREAM_STATE_STOPPING = 3, /*!< 3 */
IAV_STREAM_STATE_UNKNOWN = 255, /*!< 255 */
};
enum iav_pic_type {
IAV_PIC_TYPE_MJPEG_FRAME = 0, /*!< 0 */
IAV_PIC_TYPE_IDR_FRAME = 1, /*!< 1 */
IAV_PIC_TYPE_I_FRAME = 2, /*!< 2 */
IAV_PIC_TYPE_P_FRAME = 3, /*!< 3 */
IAV_PIC_TYPE_B_FRAME = 4, /*!< 4 */
IAV_PIC_TYPE_P_FAST_SEEK_FRAME = 5, /*!< 5 */
/* Value 6 is reseved for furture extension */
IAV_PIC_TYPE_END_FRAME = 7, /*!< 7 */
};
enum iav_statis_type {
IAV_ENC_STATIS_MV = 0x0, /*!< 0x0 */
IAV_ENC_STATIS_HEVC = 0x1, /*!< 0x1 */
IAV_ENC_STATIS_AVC = 0x2, /*!< 0x2 */
IAV_ENC_STATIS_BS_INFO = 0x3, /*!< 0x3 */
IAV_ENC_STATIS_NUM = 0x4, /*!< 0x4 */
IAV_ENC_STATIS_FIRST = IAV_ENC_STATIS_MV, /*!< IAV_ENC_STATIS_MV */
IAV_ENC_STATIS_LAST = IAV_ENC_STATIS_NUM, /*!< IAV_ENC_STATIS_NUM */
};
enum iav_desc_id {
IAV_DESC_FRAME = 0, /*!< 0, Query frame info after encoding */
IAV_DESC_STATIS = 1, /*!< 1 */
IAV_DESC_RAW = 2, /*!< 2 */
IAV_DESC_SLICE = 3, /*!< 3 */
IAV_DESC_CANVAS = 4, /*!< 4 */
IAV_DESC_PYRAMID = 5, /*!< 5 */
IAV_DESC_RAWSEQ = 6, /*!< 6 */
IAV_DESC_CANVASGRP = 7, /*!< 7 */
IAV_DESC_POLL = 8, /*!< 8 */
IAV_DESC_Y12 = 9, /*!< 9 */
IAV_DESC_BLEND_YUV = 10, /*!< 10 */
IAV_DESC_PRE_FRAME = 11, /*!< 11 */
IAV_DESC_PRE_COUNT = 12, /*!< 12 */
IAV_DESC_CUSTOM_AISP = 13, /*!< 13, Query custom aisp buf info */
IAV_DESC_RAW_SLICE = 14, /*!< 14, Query slice info of raw */
IAV_DESC_MOTION = 15, /*!< 15, Query motion data of channel */
IAV_DESC_BLEND_AREAS = 16, /*!< 16, Query blend areas */
IAV_DESC_C2Y_RAW = 17, /*!< 17, Query C2Y raw of channel */
IAV_DESC_DECI_RAW = 18, /*!< 18, Query deci raw of channel */
IAV_DESC_RAWGRP = 19, /*!< 19, Query raw of grouped VIN controllers */
IAV_DESC_NUM,
IAV_DESC_FIRST = IAV_DESC_FRAME, /*!< IAV_DESC_FRAME */
IAV_DESC_LAST = IAV_DESC_NUM, /*!< IAV_DESC_NUM */
};
enum iav_info_id {
IAV_INFO_SYSTEM = 0x00, /*!< 0x00 */
IAV_INFO_DRIVER = 0x01, /*!< 0x01 */
IAV_INFO_CANVAS = 0x02, /*!< 0x02 */
IAV_INFO_STREAM = 0x03, /*!< 0x03 */
IAV_INFO_MASK = 0x04, /*!< 0x04 */
IAV_INFO_BSB_STATS = 0x05, /*!< 0x05 */
IAV_INFO_WAFER_ID = 0x06, /*!< 0x06 */
IAV_INFO_UNIQUE_ID = 0x07, /*!< 0x07 */
IAV_INFO_AUDIT = 0x08, /*!< 0x08 */
IAV_INFO_CHANNEL = 0X09, /*!< 0x09 */
IAV_INFO_DSP_HEALTH = 0x0A, /*!< 0x0A */
IAV_INFO_PREV_PARAMS = 0x0B, /*!< 0x0B */
IAV_INFO_IDLE_PARAMS = 0x0C, /*!< 0x0C */
IAV_INFO_NUM = 0x0D, /*!< 0x0D */
};
enum iav_dsp_health_status {
DSP_HEALTH_STATUS_DISABLED = 0x00, /*!< 0x00 */
DSP_HEALTH_STATUS_NORMAL = 0x01, /*!< 0x01 */
DSP_HEALTH_STATUS_VCAP_HANG = 0x02, /*!< 0x02 */
DSP_HEALTH_STATUS_ASSERT = 0x03, /*!< 0x03 */
DSP_HEALTH_STATUS_INVALID_CLKS = 0x04, /*!< 0x04 */
DSP_HEALTH_STATUS_PERF_DROP = 0x05, /*!< 0x05 */
DSP_HEALTH_STATUS_NUM = 0x06, /*!< 0x06 */
DSP_HEALTH_STATUS_FIRST = DSP_HEALTH_STATUS_DISABLED, /*!< DSP_HEALTH_STATUS_DISABLED */
DSP_HEALTH_STATUS_LAST = DSP_HEALTH_STATUS_NUM, /*!< DSP_HEALTH_STATUS_NUM */
};
enum iav_bsb_mode {
IAV_STRM_SHR_BSB = 0x0, /*!< user app and DSP share the same BSB buffer */
IAV_STRM_INDIV_BSB = 0x1, /*!< user app and DSP have their own BSB buffer separately */
};
enum iav_hdr_type {
HDR_TYPE_OFF = 0, /*!< 0 */
HDR_TYPE_BASIC = 1, /*!< 1 */
HDR_TYPE_ADV_WITH_CE = 2, /*!< 2 */
HDR_TYPE_TOTAL_NUM = 3, /*!< 3 */
};
enum iav_iso_type {
ISO_TYPE_LOW = 0, /*!< 0 */
ISO_TYPE_MIDDLE = 1, /*!< 1 */
ISO_TYPE_ADVANCED = 2, /*!< 2 */
ISO_TYPE_AISP = 3, /*!< 3 */
ISO_TYPE_CUSTOM_AISP = 4, /*!< 4 */
ISO_TYPE_TOTAL_NUM = 5, /*!< 5 */
};
enum iav_max_vwarp_waitlines_count {
VWARP_WAITLINES_MIN = 0, /*!< 0 */
VWARP_WAITLINES_LDC_DEFAULT = 64, /*!< 64 */
VWARP_WAITLINES_MAX = 1023, /*!< 1023 */
};
enum iav_max_vwarp_blk_height {
VWARP_BLK_HEIGHT_MIN = 28, /*!< 28 */
VWARP_BLK_HEIGHT_MAX = 64, /*!< 64 */
};
enum iav_eis_delay_count {
EIS_DELAY_COUNT_OFF = 0, /*!< 0 */
EIS_DELAY_COUNT_MIN = 1, /*!< 1 */
EIS_DELAY_COUNT_GOLDEN = 3, /*!< 3 */
EIS_DELAY_COUNT_MAX = 64, /*!< 64 */
};
enum iav_ce_go_map_delay_count {
GO_MAP_DELAY_COUNT_OFF = 0, /*!< 0 */
GO_MAP_DELAY_COUNT_MIN = 1, /*!< 1 */
GO_MAP_DELAY_COUNT_GOLDEN = 3, /*!< 3 */
GO_MAP_DELAY_COUNT_MAX = 7, /*!< 7 */
};
enum iav_me0_scale {
ME0_SCALE_OFF = 0, /*!< 0 */
ME0_SCALE_8X = 1, /*!< 1 */
ME0_SCALE_16X = 2, /*!< 2 */
ME0_SCALE_TOTAL_NUM = 3, /*!< 3 */
};
enum iav_srcbuf_id {
IAV_SRCBUF_MN = 0, /*!< 0, main buffer */
IAV_SRCBUF_PC = 1, /*!< 1, 2nd buffer */
IAV_SRCBUF_PB = 2, /*!< 2, 3rd buffer */
IAV_SRCBUF_PA = 3, /*!< 3, 4th buffer */
IAV_SRCBUF_PD = 4, /*!< 4, 5th buffer */
IAV_SRCBUF_PE = 5, /*!< 5, 6th buffer */
IAV_SRCBUF_PF = 6, /*!< 6, 7th buffer, only for IR output or C2Y RAW output */
IAV_SRCBUF_PMN = 7, /*!< 7, virtual pre-main buffer, only for dewarp mode */
IAV_SRCBUF_NUM = 8, /*!< 8 */
IAV_SRCBUF_EFM = 24, /*!< 24, EFM buffer ID for both single and multi VIN */
/* For user space convenience */
IAV_SRCBUF_1 = IAV_SRCBUF_MN, /*!< IAV_SRCBUF_MN */
IAV_SRCBUF_2 = IAV_SRCBUF_PC, /*!< IAV_SRCBUF_PC */
IAV_SRCBUF_3 = IAV_SRCBUF_PB, /*!< IAV_SRCBUF_PB */
IAV_SRCBUF_4 = IAV_SRCBUF_PA, /*!< IAV_SRCBUF_PA */
IAV_SRCBUF_5 = IAV_SRCBUF_PD, /*!< IAV_SRCBUF_PD */
IAV_SRCBUF_6 = IAV_SRCBUF_PE, /*!< IAV_SRCBUF_PE */
IAV_SRCBUF_7 = IAV_SRCBUF_PF, /*!< IAV_SRCBUF_PF */
IAV_SRCBUF_FIRST = IAV_SRCBUF_MN, /*!< IAV_SRCBUF_MN */
IAV_SRCBUF_LAST = IAV_SRCBUF_PMN, /*!< IAV_SRCBUF_PMN */
IAV_SRCBUF_LAST_PMN = IAV_SRCBUF_PMN + 1, /*!< IAV_SRCBUF_PMN + 1 */
IAV_SUB_SRCBUF_FIRST = IAV_SRCBUF_PC, /*!< IAV_SRCBUF_PC */
IAV_SUB_SRCBUF_LAST = IAV_SRCBUF_PMN, /*!< IAV_SRCBUF_PMN */
IAV_WARP_DPTZ_BUF_NUM = 6, /*!< 6 */
IAV_MAINBUF_INPUT_WIDTH_ALIGN = 8, /*!< 8 */
IAV_MAINBUF_INPUT_HEIGHT_ALIGN = 8, /*!< 8 */
IAV_MAINBUF_INPUT_OFFSET_ALIGN = 4, /*!< 4 */
IAV_MAINBUF_OUTPUT_WIDTH_ALIGN = 32, /*!< 32 */
IAV_MAINBUF_OUTPUT_WIDTH_ROTATE_ALIGN = 32, /*!< 32 */
IAV_MAINBUF_OUTPUT_HEIGHT_ALIGN = 16, /*!< 16 */
IAV_SUBBUF_INPUT_H_ALIGN = 4, /*!< 4 */
IAV_SUBBUF_INPUT_V_ALIGN = 2, /*!< 2 */
IAV_SRCBUF_OUTPUT_X_ALIGN = 2, /*!< 2 */
IAV_SRCBUF_OUTPUT_Y_ALIGN = 4, /*!< 4 */
IAV_SRCBUF_OUTPUT_WIDTH_ALIGN = 32, /*!< 32 */
IAV_SRCBUF_OUTPUT_HEIGHT_ALIGN = 16, /*!< 16 */
};
enum iav_codec_option {
IAV_CODEC_H265_H264_MJPEG = 0x0, /*!< 0x0 */
IAV_CODEC_H265_MJPEG = 0x1, /*!< 0x1 */
IAV_CODEC_H264_MJPEG = 0x2, /*!< 0x2 */
IAV_CODEC_MJPEG_ONLY = 0x3, /*!< 0x3 */
IAV_CODEC_TOTAL_NUM = 0x4, /*!< 0x4 */
};
enum iav_system_params {
IAV_MAX_CANVAS_BUF_NUM_IMPL = 12, /*!< 12 */
IAV_MAX_CANVAS_BUF_NUM_EXTRA = 8, /*!< 8 */
IAV_MAX_CANVAS_BUF_NUM = (IAV_MAX_CANVAS_BUF_NUM_IMPL + IAV_MAX_CANVAS_BUF_NUM_EXTRA), /*!< IAV_MAX_CANVAS_BUF_NUM_IMPL + IAV_MAX_CANVAS_BUF_NUM_EXTRA */
IAV_STREAM_MAX_NUM_IMPL = 12, /*!< 12 */
IAV_STREAM_MAX_NUM_EXTRA = 8, /*!< 8 */
IAV_STREAM_MAX_NUM_ALL = (IAV_STREAM_MAX_NUM_IMPL + IAV_STREAM_MAX_NUM_EXTRA), /*!< IAV_STREAM_MAX_NUM_IMPL + IAV_STREAM_MAX_NUM_EXTRA */
};
enum iav_debug_type {
DEBUG_TYPE_CHIP_ID = (1 << 0), /*!< 1 << 0 */
DEBUG_TYPE_BREAK_POINT = (1 << 1), /*!< 1 << 1 */
DEBUG_TYPE_HEVC_ENC_MODE = (1 << 2), /*!< 1 << 2 */
DEBUG_TYPE_VSYNC_LOSS_TIMEOUT = (1 << 3), /*!< 1 << 3 */
DEBUG_TYPE_MAX_CHROMA_RADIUS = (1 << 4), /*!< 1 << 4 */
DEBUG_TYPE_CE_OFF = (1 << 5), /*!< 1 << 5 */
DEBUG_TYPE_PERF_OPT_ENABLE = (1 << 6), /*!< 1 << 6 */
DEBUG_TYPE_LOW_DELAY_ENABLE = (1 << 7), /*!< 1 << 7 */
DEBUG_TYPE_PREBLEND_ONLY_FOR_AISP = (1 << 8), /*!< 1 << 8 */
DEBUG_TYPE_MAX_SLICE_NUM = (1 << 9), /*!< 1 << 9 */
DEBUG_TYPE_CHAN_GROUP_TOLERANCE = (1 << 10), /*!< 1 << 10 */
DEBUG_TYPE_OVERLAY_BLUR_CACHE_CMD_NUM_MINUS_2 = (1 << 11), /*!< 1 << 11 */
DEBUG_TYPE_AISP_PIPE_MODE = (1 << 12), /*!< 1 << 12 */
DEBUG_TYPE_HEART_BEAT_INTVAL_TIME = (1 << 13), /*!< 1 << 13 */
};
/*! @enum iav_vsync_loss_timeout
* @brief vsync loss timeout limitation on milli second unit.
* Usually, it's mainly used for debug purpose.
*/
enum iav_vsync_loss_timeout {
IAV_VSYNC_LOSS_TIMEOUT_MIN = 32, /*!< 32 ms */
IAV_VSYNC_LOSS_TIMEOUT_DEFAULT = 2048, /*!< 2048 ms */
IAV_VSYNC_LOSS_TIMEOUT_MAX = 4095, /*!< 4095 ms */
};
/*! @enum iav_extra_raw_dram_buf
* @brief iav extra raw dram buffer limitation. Default is zero.
* Usually, it's mainly used for debug purpose. The larger extra buffer, DSP
* takes more DRAM footprint and can save more RAW images into memory.
*/
enum iav_extra_raw_dram_buf {
IAV_EXTRA_RAW_DRAM_BUF_MIN = 0,
IAV_EXTRA_RAW_DRAM_BUF_MAX = 128,
};
enum iav_enc_dummy_latency {
IAV_ENC_DUMMY_LATENCY_MIN = 0,
IAV_ENC_DUMMY_LATENCY_MAX = 15,
};
#define IAV_INVALID_CANVAS_ID (0xFF)
#define IAV_INVALID_CHAN_ID (0xFF)
#define IAV_INVALID_RAW_ENC_BUF_ID (0xFF)
enum iav_pyramid_scale {
IAV_PYRAMID_SCALE_SQRT2 = 0, /*!< 0, 1/sqrt(2) for each layers, both width and height */
IAV_PYRAMID_SCALE_2X = 1, /*!< 1, 1/2 for each layers, both width and height */
IAV_PYRAMID_SCALE_ARBITRARY = 2, /*!< 2, arbitrary size for pyramid layer 1 */
};
enum iav_sync_type {
IAV_FRAME_SYNC = 0, /*!< 0 */
IAV_STREAM_SYNC = 1, /*!< 1 */
IAV_IDSP_ENC_SYNC = 2, /*!< 2 */
IAV_NONE_SYNC = 3, /*!< 3 */
IAV_CANVAS_SYNC = 4, /*!< 4 */
IAV_EFM_FRAME_SYNC = 5, /*!< 5 */
IAV_SYNC_TYPE_NUM = 6, /*!< 6 */
};
enum iav_manual_feed_type {
IAV_MANUAL_FEED_CANVAS = 0, /*!< 0 */
IAV_MANUAL_FEED_PYRAMID = 1, /*!< 1 */
IAV_MANUAL_FEED_RAW = 2, /*!< 2 */
IAV_MANUAL_FEED_NUM = 3, /*!< 3 */
};
enum iav_yuv_format {
IAV_YUV_FORMAT_YUV422 = 0, /*!< 0 */
IAV_YUV_FORMAT_YUV420 = 1, /*!< 1 */
IAV_YUV_FORMAT_YUV400 = 2, /*!< 2 */
};
#define IAV_IMG_SCALE_H_ALIGN (4)
#define IAV_IMG_SCALE_V_ALIGN (2)
#define IAV_IMG_SCALE_Q_DEPTH_MAX (16)
#define IAV_IMG_SCALE_Q_DEPTH_MIN (8)
#define IAV_IMG_SCALE_HEIGHT_MIN (64)
enum iav_chroma_radius_num {
CHROMA_RADIUS_32 = 0, /*!< 0 */
CHROMA_RADIUS_64 = 1, /*!< 1 */
CHROMA_RADIUS_128 = 2, /*!< 2 */
CHROMA_RADIUS_TOTAL_NUM,
};
/*! @enum iav_app_img_profile
* @brief Application image 3A profile enum.
*/
enum iav_app_img_profile {
APP_IMG_PROFILE_IPC = 0, /*!< 0 */
APP_IMG_PROFILE_BWC = 1, /*!< 1 */
APP_IMG_PROFILE_ITS = 2, /*!< 2 */
APP_IMG_PROFILE_DVR = 3, /*!< 3 */
APP_IMG_PROFILE_DMS = 4, /*!< 4 */
APP_IMG_PROFILE_ADAS = 5, /*!< 5 */
APP_IMG_PROFILE_OMC = 6, /*!< 6 */
APP_IMG_PROFILE_EMIRROR = 7, /*!< 7 */
APP_IMG_PROFILE_STEREO = 8, /*!< 8 */
APP_IMG_PROFILE_BYPASS_ISP = 9, /*!< 9 */
APP_IMG_PROFILE_ROBOT = 10, /*!< 10 */
APP_IMG_PROFILE_ACC = 11, /*!< 11 */
APP_IMG_PROFILE_NUM,
APP_IMG_PROFILE_FIRST = APP_IMG_PROFILE_IPC, /*!< APP_IMG_PROFILE_IPC */
APP_IMG_PROFILE_LAST = APP_IMG_PROFILE_NUM, /*!< APP_IMG_PROFILE_NUM */
};
enum iav_idsp_core_mode {
IAV_IDSP_CORE_0 = 0, /*!< 0 */
IAV_IDSP_CORE_1 = 1, /*!< 1 */
IAV_IDSP_DUAL_CORE = 2, /*!< 2 */
IAV_IDSP_CORE_MODE_NUM, /*!< Total number of idsp core mode */
};
enum iav_enc_core_mode {
IAV_ENC_CORE_0 = 0, /*!< 0 */
IAV_ENC_CORE_1 = 1, /*!< 1 */
IAV_ENC_DUAL_CORE_TEMPORAL = 2, /*!< 2 */
IAV_ENC_DUAL_CORE_SPATIAL = 3, /*!< 3 */
IAV_ENC_CORE_MODE_NUM, /*!< Total number of encoder core mode */
};
enum iav_overlay_pixel_format {
IAV_OVERLAY_FORMAT_8BIT_CLUT8 = 0,
IAV_OVERLAY_FORMAT_8BIT_LAST = 1,
IAV_OVERLAY_FORMAT_8BIT_FIRST = IAV_OVERLAY_FORMAT_8BIT_CLUT8,
IAV_OVERLAY_FORMAT_16BIT_RGB565 = 1, /* 5:6:5 (RGB) */
IAV_OVERLAY_FORMAT_16BIT_UYV565 = 2, /* 5:6:5 (UYV) or (BGR) */
IAV_OVERLAY_FORMAT_16BIT_BGR565 = 3,
IAV_OVERLAY_FORMAT_16BIT_AYUV4444 = 4, /* 4:4:4:4 (AYUV) */
IAV_OVERLAY_FORMAT_16BIT_RGBA4444 = 5, /* 4:4:4:4 (RGBA) */
IAV_OVERLAY_FORMAT_16BIT_BGRA4444 = 6, /* 4:4:4:4 (BGRA) */
IAV_OVERLAY_FORMAT_16BIT_ABGR4444 = 7, /* 4:4:4:4 (ABGR) */
IAV_OVERLAY_FORMAT_16BIT_ARGB4444 = 8, /* 4:4:4:4 (ARGB) */
IAV_OVERLAY_FORMAT_16BIT_AYUV1555 = 9, /* 1:5:5:5 (AYUV) */
IAV_OVERLAY_FORMAT_16BIT_YUV1555 = 10, /* 1:5:5:5 (MSB ignored, YUV) */
IAV_OVERLAY_FORMAT_16BIT_RGBA5551 = 11, /* 5:5:5:1 (RGBA) */
IAV_OVERLAY_FORMAT_16BIT_BGRA5551 = 12, /* 5:5:5:1 (BGRA) */
IAV_OVERLAY_FORMAT_16BIT_ABGR1555 = 13, /* 1:5:5:5 (ABGR) */
IAV_OVERLAY_FORMAT_16BIT_ARGB1555 = 14, /* 1:5:5:5 (ARGB) */
IAV_OVERLAY_FORMAT_16BIT_LAST = 15,
IAV_OVERLAY_FORMAT_16BIT_FIRST = IAV_OVERLAY_FORMAT_16BIT_RGB565,
IAV_OVERLAY_FORMAT_32BIT_AYUV8888 = 15, /* 8:8:8:8 (AYUV) */
IAV_OVERLAY_FORMAT_32BIT_RGBA8888 = 16, /* 8:8:8:8 (RGBA) */
IAV_OVERLAY_FORMAT_32BIT_BGRA8888 = 17, /* 8:8:8:8 (BGRA) */
IAV_OVERLAY_FORMAT_32BIT_ABGR8888 = 18, /* 8:8:8:8 (ABGR) */
IAV_OVERLAY_FORMAT_32BIT_ARGB8888 = 19, /* 8:8:8:8 (ARGB) */
IAV_OVERLAY_FORMAT_32BIT_LAST = 20,
IAV_OVERLAY_FORMAT_32BIT_FIRST = IAV_OVERLAY_FORMAT_32BIT_AYUV8888,
IAV_OVERLAY_FORMAT_INVALID = 0xFF,
};
#define IAV_GDMA_MAX_WIDTH (4096)
enum IAV_BUFCAP_FLAG {
IAV_BUFCAP_NONBLOCK = (1 << 0), /*!< 1 << 0 */
};
enum IAV_CHAN_INPUT_SRC {
IAV_CHAN_INPUT_SRC_RAW = 0, /*!<0 */
IAV_CHAN_INPUT_SRC_CE = 1, /*!< 1 */
IAV_CHAN_INPUT_SRC_LOW_RES = 2, /*!< 2 */
IAV_CHAN_INPUT_SRC_NUM = 3, /*!< 3 */
};
enum IAV_RAW_FORMAT {
IAV_RAW_FORMAT_RGB = 0, /*!<0 */
IAV_RAW_FORMAT_YUV422 = 1, /*!< 1 */
IAV_RAW_FORMAT_YUV420 = 2, /*!< 2 */
};
enum IAV_C2Y_RAW_FORMAT {
IAV_C2Y_RAW_FORMAT_AUTO = 0, /*!< 0, Automatically decided by IAV. */
IAV_C2Y_RAW_FORMAT_8_BITS = 1, /*!< 1, 8bits per pixel. */
IAV_C2Y_RAW_FORMAT_16_BITS = 2, /*!< 2, 16bits per pixel. */
IAV_C2Y_RAW_FORMAT_CMPR = 3, /*!< 3, compressed format. */
IAV_C2Y_RAW_FORMAT_NUM,
};
enum IAV_BLEND_AREA {
IAV_BLEND_LEFT_OR_TOP = 0, /*!< 0, This stands for left channel or top channel. */
IAV_BLEND_RIGHT_OR_BOT = 1, /*!< 1, This stands for right channel or bottom channel. */
IAV_BLEND_NUM = 2, /*!< 2 */
IAV_BLEND_INVALID = 0xFF, /*!< 0xFF */
};
enum IAV_BLEND_PARAM {
IAV_BLEND_NONBLOCK = (1 << 0), /*!< 1 << 0 */
IAV_BLEND_ALPHA_ADDR_INVALID = 0xFFFFFFFF, /*!< 0xFFFFFFFF */
IAV_BLEND_WARP_ADDR_INVALID = 0xFFFFFFFF, /*!< 0xFFFFFFFF */
IAV_BLEND_OVERLAP_AREA_MAX = 12, /*!< 12. Maximum overlap area number. */
};
enum IAV_BLEND_TYPE {
IAV_BLEND_TYPE_NONE = 0, /*!< 0 */
IAV_BLEND_TYPE_HOR = 1, /*!< 1, This is to specify multi-channel stitched horizontally (Left & Right). */
IAV_BLEND_TYPE_VER = 2, /*!< 2, This is to specify multi-channel stitched vertically (Top & Bottom). */
IAV_BLEND_TYPE_NUM, /*!< 3 */
IAV_BLEND_TYPE_FIRST = IAV_BLEND_TYPE_NONE, /*!< IAV_BLEND_TYPE_NONE */
IAV_BLEND_TYPE_LAST = IAV_BLEND_TYPE_NUM, /*!< IAV_BLEND_TYPE_NUM */
};
enum iav_audit_cfg_id {
IAV_AUDIT_ISR_DURATION = 0,
IAV_AUDIT_ISR_INTERVAL = 1,
IAV_AUDIT_IAV_IOCTL = 2,
IAV_AUDIT_IMGPROC_IOCTL = 3,
IAV_AUDIT_YUV_DELAY = 4,
IAV_AUDIT_ENC_DELAY = 5,
IAV_AUDIT_VV_DELAY = 6,
IAV_AUDIT_IDSP = 7,
IAV_AUDIT_ENC = 8,
IAV_AUDIT_VOUT = 9,
IAV_AUDIT_ENC_SYNC = 10,
IAV_AUDIT_EIS_SYNC = 11,
IAV_AUDIT_IMG_SCALER = 12,
IAV_AUDIT_ENC_CLK = 13,
IAV_AUDIT_FRAME_SYNC = 14,
IAV_AUDIT_DEWARP_PROC = 15,
IAV_AUDIT_IAV_EVENT_TIME = 16,
IAV_AUDIT_IDSP_SYNC = 17,
IAV_AUDIT_C2Y_SYNC = 18,
IAV_AUDIT_NUM = 19,
IAV_AUDIT_FIRST = IAV_AUDIT_ISR_DURATION, /*!< IAV_AUDIT_ISR_DURATION */
IAV_AUDIT_LAST = IAV_AUDIT_NUM, /*!< IAV_AUDIT_NUM */
};
enum iav_vout_underflow_prevention {
IAV_VOUT_UNDERFLOW_PREVENTION_MIN = 0,
IAV_VOUT_UNDERFLOW_PREVENTION_MAX = 4,
};
enum iav_chan_group_tolerance {
IAV_CHAN_GROUP_TOLERANCE_MIN = 1,
IAV_CHAN_GROUP_TOLERANCE_MAX = 100,
};
enum iav_overlay_blur_cache_cmd_num_minus_2 {
IAV_OVERLAY_BLUR_CACHE_CMD_NUM_MINUS_2_MIN = 0,
IAV_OVERLAY_BLUR_CACHE_CMD_NUM_MINUS_2_MAX = 3,
};
enum iav_ir_output_type {
IAV_IR_OUT_TYPE_DISABLE = 0,
IAV_IR_OUT_TYPE_FULL = 1,
IAV_IR_OUT_TYPE_2H2V = 2,
IAV_IR_OUT_TYPE_NUM = 3,
};
/*! @enum iav_vsync_loss_pm_delay
* @brief vsync loss dummy frame pm cover delay time limitation on milli second unit.
*/
enum iav_vsync_loss_pm_delay {
IAV_VSYNC_LOSS_PM_DELAY_MIN = 0, /*!< 0 ms */
IAV_VSYNC_LOSS_PM_DELAY_MAX = 60000, /*!< 60000 ms */
IAV_VSYNC_LOSS_PM_DISABLE = 65535, /*!< disable PM cover */
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
typedef union {
struct {
u32 hdmi_field : 1; /*!< hdmi field, 0-outputting even field, 1-outputting odd field */
u32 analog_field : 1; /*!< analog field, 0-outputting even field, 1-outputting odd field */
u32 digital_field : 1; /*!< digital field, 0-outputting even field, 1-outputting odd field */
u32 mipi_error : 1;
u32 gamma_configuration_ready : 1;
u32 mipi_fifo_overflow : 1; /*!< mipi fifo overflow */
u32 watchdog_timeout : 1; /*!< dispaly watchdog timeout */
u32 reserved : 18;
u32 digital_656_shifted_right : 1; /*!< if an unwanted right shift has happened */
u32 digital_656_shifted_left : 1; /*!< if an unwanted left shift has happened */
u32 hdmi_underflow : 1; /*!< hdmi underflow */
u32 analog_underflow : 1; /*!< analog underflow */
u32 digital_underflow : 1; /*!< digital underflow */
u32 sdtv_configuration_ready : 1;
u32 reset_display_section_ready : 1;
};
u32 val;
} iav_vout_status_t;
struct iav_system_info {
u16 query_source; /*!< Query Source ID, @sa iav_system_query_source */
u16 boot_mode; /*!< System Boot Mode, @sa iav_boot_mode */
u16 reserved[2];
};
struct iav_canvas_info {
u32 canvas_id : 8; /*!< Canvas ID */
u32 is_broken : 1; /* Canvas is broken or not. */
u32 reserved0 : 7;
u32 chan_map : 16; /*!< The channel map for source buffers in this canvas */
enum iav_canvas_type type; /*!< Canvas Type enumeration, @sa iav_canvas_type */
enum iav_canvas_state state; /*!< Canvas State enumeration, @sa iav_canvas_state */
u32 reserved1;
unsigned long mem_phys_addr; /*!< Canvas memory partition base physical address */
unsigned long mem_size; /*!< Canvas memory partition size */
u16 width; /*!< Canvas width */
u16 height; /*!< Canvas height */
u16 yuv_pitch; /*!< Canvas YUV pitch */
u16 me1_pitch; /*!< Canvas ME1 pitch */
u16 me0_pitch; /*!< Canvas ME0 pitch */
u16 reserved2[3];
};
struct iav_stream_info {
u32 id; /*!< Stream ID */
enum iav_stream_state state; /*!< Stream State enumeration, @sa iav_stream_state */
};
struct iav_privacy_mask_info {
u8 channel_id; /*!< Specify the channel ID to get privacy mask information */
u8 multi_factor; /*!< It reports the privacy mask buffer to Main buffer scaling factor */
u16 buffer_width; /*!< It reports the privacy mask buffer width */
u16 buffer_height; /*!< It reports the privacy mask buffer height */
u16 buffer_pitch; /*!< It reports the privacy mask buffer pitch */
};
struct iav_bsb_stats_info {
enum iav_bsb_mode bsb_mode; /*!< BSB mode. @ref iav_bsb_mode */
u32 bsb_overflow_discarded_cnt[IAV_STREAM_MAX_NUM_ALL]; /*!< discarded frame count due to BSB overflow */
union {
u32 free_kbytes; /*!< free kbytes of BSB for shared BSB mode*/
u32 free_kbytes_per_stream[IAV_STREAM_MAX_NUM_ALL]; /*!< free kbytes of BSB per stream for individual BSB mode*/
};
u32 reserved[7]; /*!< Align to 192Byte when "IAV_STREAM_MAX_NUM_ALL == 20" */
};
struct iav_channel_info {
u8 channel_id; /*!< Specify the channel ID to get channel information */
u8 slice_num; /*!< It reports the slice number for this channel */
u8 reserved[2];
};
struct iav_unique_id {
u8 unique_id[UNIQUE_ID_SIZE]; /*!< dsp unique ID */
};
struct iav_audit_cfg {
enum iav_audit_cfg_id audit_cfg_id; /*!< Audit config id enumeration. @sa iav_audit_cfg_id*/
u32 enable : 1; /*!< Flag to indicate that the purpose of the operation is to enable or disable audit. */
u32 reserved0 : 31;
u32 audit_cfg_map; /*!< The second-level type index map of audit config type. */
u32 reserved1[13]; /*!< Align to 64Byte. */
};
struct iav_audit {
u32 id; /*!< The index of the specified audit config */
u32 enable : 1; /*!< Flag to indicate the audit status */
u32 reserved0 : 31;
u64 cnt; /*!< The count of audit triggered */
u64 sum; /*!< The sum of all delay audits times */
u32 max; /*!< The maximum time in all delay audits */
u32 min; /*!< The minimum time in all delay audits */
u32 cur; /*!< The current delay time being audited */
u32 reserved1;
u64 sys_time; /*!< The current system time being audited. */
};
struct iav_idsp_audit {
u32 enable : 1; /*!< Enable/Disable idsp frame drop and group discard audit. */
u32 reserved : 31;
u32 idsp_frm_drop_cnt[IAV_MAX_CHANNEL_NUM]; /*!< idsp frame drop count. Each time when this audit is enabled, it will be reset to 0. */
u32 idsp_grouping_frame_discard_cnt[IAV_MAX_CHANNEL_NUM]; /*!< idsp channel group frame discard count.
Each time when this audit is enabled, it will be reset to 0. */
};
struct iav_enc_audit {
u32 enable : 1; /*!< Enable/Disable encode frame drop audit. it only audits the frame drop count due to BO check. */
u32 reserved : 31;
u32 enc_frm_drop_cnt[IAV_STREAM_MAX_NUM_ALL]; /*!< encode frame drop count. Each time when this audit is enabled, it will be reset to 0. */
};
struct iav_vout_audit {
u32 enable : 1; /*!< Enable/Disable vout underflow and osd sync fail audit. */
u32 reserved : 31;
u32 vout_drop_cnt[VOUT_NUM]; /*!< vout drop count. Each time when this audit is enabled, it will be reset to 0. */
u32 osd_sync_fail_cnt[VOUT_NUM]; /*!< vout osd sync fail count. Each time when this audit is enabled, it will be reset to 0. */
};
struct iav_enc_sync_audit {
u32 enable : 1; /*!< Enable/Disable encode sync fail audit. */
u32 reserved : 31;
u32 frame_sync_fail_cnt[IAV_STREAM_MAX_NUM_ALL]; /*!< encode frame sync fail count. Each time when this audit is enabled, it will be reset to 0. */
u32 frame_sync_total_cnt[IAV_STREAM_MAX_NUM_ALL]; /*!< encode frame sync total count. Each time when this audit is enabled, it will be reset to 0. */
u32 stream_sync_fail_cnt[IAV_STREAM_MAX_NUM_ALL]; /*!< encode stream sync fail count. Each time when this audit is enabled, it will be reset to 0. */
u32 stream_sync_total_cnt[IAV_STREAM_MAX_NUM_ALL]; /*!< encode stream sync total count. Each time when this audit is enabled, it will be reset to 0. */
};
struct iav_frame_sync_audit {
u32 enable : 1; /*!< Enable/Disable sync fail audit. */
u32 reserved : 31;
u32 overlay_sync_fail_cnt; /*!< overlay sync fail cnt. */
u32 blur_sync_fail_cnt; /*!< blur sync fail cnt. */
u32 yuv_remap_sync_fail_cnt; /*!< yuv remap sync fail cnt. */
u32 overlay_sync_total_cnt; /*!< overlay sync total cnt. */
u32 blur_sync_total_cnt; /*!< blur sync total cnt. */
u32 yuv_remap_sync_total_cnt; /*!< yuv remap sync total cnt. */
};
struct iav_c2y_sync_audit {
u32 enable : 1; /*!< Enable/Disable sync fail audit. */
u32 reserved : 31;
u32 ce_go_map_sync_fail_cnt[IAV_MAX_CHANNEL_NUM]; /*!< Software CE gain offset map sync fail count.
Each time when this audit is enabled, it will be reset to 0. */
u32 ce_go_map_sync_total_cnt[IAV_MAX_CHANNEL_NUM]; /*!< Software CE gain offset map sync total count.
Each time when this audit is enabled, it will be reset to 0. */
};
struct iav_eis_audit {
u32 enable : 1; /*!< Enable/Disable EIS warp sync fail audit. */
u32 reserved : 31;
u32 sync_fail_cnt[IAV_MAX_CHANNEL_NUM]; /*!< EIS warp sync fail count.
Each time when this audit is enabled, it will be reset to 0. */
u32 sync_total_cnt[IAV_MAX_CHANNEL_NUM]; /*!< EIS warp sync total count.
Each time when this audit is enabled, it will be reset to 0. */
};
struct iav_idsp_sync_audit {
u32 enable : 1; /*!< Enable/Disable EIS warp sync fail audit. */
u32 reserved : 31;
u32 sync_fail_cnt[IAV_MAX_CHANNEL_NUM]; /*!< idsp sync fail count.
Each time when this audit is enabled, it will be reset to 0. */
u32 sync_total_cnt[IAV_MAX_CHANNEL_NUM]; /*!< idsp sync total count.
Each time when this audit is enabled, it will be reset to 0. */
};
struct iav_multi_region_warp_pixel_audit {
u32 enable : 1; /*!< Enable/Disable multi-region warp area audit. */
u32 reserved : 31;
u32 reserved1;
u64 total_warp_pixels[IAV_MAX_CHANNEL_NUM]; /*!< Pixel amount of warp region processed in IDSP. */
u64 total_warp_pixels_max[IAV_MAX_CHANNEL_NUM]; /*!< Maximum pixel amount of warp region processed in IDSP previously. */
};
struct iav_event_time_audit {
u32 enable : 1; /*!< Enable/Disable system events duration audit. */
u32 reserved : 31;
u32 reserved1;
u64 enter_preview_time; /*!< The latest time consumed for the iav to switch from the idle state to the preview state. unit:us. */
u64 enter_idle_time; /*!< The latest time consumed for the iav to switch from the preview state to the idle state. unit:us. */
u64 enc_start_time[IAV_STREAM_MAX_NUM_ALL]; /*!< The latest time consumed for the stream to start up. unit:us. */
u64 enc_stop_time[IAV_STREAM_MAX_NUM_ALL]; /*!< The latest time consumed for the stream to stop. unit:us. */
};
struct iav_audit_info {
enum iav_audit_cfg_id cid; /*!< audit configuration item ID */
u32 cfg_map; /*!< The second-level type index map to specify when querying some statistics */
union {
struct iav_audit int_delay[IAV_DSP_AUDIT_INT_NUM]; /*!< IAV interrupt delay audit info */
struct iav_idsp_audit idsp; /*!< IAV IDSP frame drop audit info */
struct iav_enc_audit enc; /*!< IAV encode frame drop audit info */
struct iav_vout_audit vout; /*!< IAV vout underflow audit info */
struct iav_enc_sync_audit enc_sync; /*!< Encode frame sync and stream sync fail audit info */
struct iav_audit vv_delay[VOUT_NUM]; /*!< VOUT-VIN delay audit info */
struct iav_audit enc_delay[IAV_STREAM_MAX_NUM_ALL]; /*!< encode delay audit info */
struct iav_audit idsp_delay[IAV_MAX_CANVAS_BUF_NUM];/*!< idsp delay audit info */
struct iav_audit enc_clk; /*!< Encode clock audit info */
struct iav_audit img_scaler; /*!< Img scaler audit info */
struct iav_frame_sync_audit frame_sync; /*!< Frame sync for overlay / blur /YUV remap fail audit info */
struct iav_eis_audit eis; /*!< EIS warp sync fail audit info */
struct iav_idsp_sync_audit idsp_sync; /*!< Idsp sync fail audit info */
struct iav_multi_region_warp_pixel_audit multi_region_warp; /*!< multi-region warp pixel audit info */
struct iav_event_time_audit event_time_audit; /*!< IAV event time audit info, such as preview / idle time,
and encode start / stop time. */
struct iav_c2y_sync_audit c2y_sync; /*!< C2Y sync for CE go map fail audit info */
} arg; /*!< IAV audit configuration */
};
struct iav_dsp_health_cfg {
u32 enable : 1; /*!< Flag to enable or disable DSP health guard. */
u32 reserved0 : 15;
u32 check_interval : 8; /*!< the checking interval in seconds */
u32 frame_drop_tolerance : 8; /*!< the frame drop tolerance in frames per second */
u32 reserved[3]; /*!< aligned to 12Byte */
};
struct iav_dsp_health_info {
enum iav_dsp_health_status status; /*!< the dsp health status */
u32 reserved[3]; /*!< aligned to 12Byte */
};
struct iav_queryinfo {
enum iav_info_id qid;
union {
struct iav_system_info system_info; /*!< Query system info */
struct iav_driver_version driver; /*!< Query driver version */
struct iav_canvas_info canvas; /*!< Query canvas info, such as state / type */
struct iav_stream_info stream; /*!< Query stream info, such as state */
struct iav_privacy_mask_info mask_info; /*!< Query privacy mask info */
struct iav_bsb_stats_info bsb_stats; /*!< Query BSB statistic info */
struct iav_unique_id unique_id; /*!< Query unique ID */
struct iav_audit_info audit; /*!< Query audit info */
struct iav_channel_info chan_info; /*!< Query channel info, such as slice number */
struct iav_dsp_health_info dsp_health_info; /*!< Query DSP health info */
u64 chip_wafer_id; /*!< Query Chip Unique Wafer ID */
struct iav_preview_params prev_params; /*!< Query iav preview parameters info */
struct iav_idle_params idle_params; /*!< Query iav idle parameters info */
} arg;
};
struct iav_img_scale_cfg {
u8 enable : 1; /*!< This is a flag to enable img scale */
u8 format : 2; /*!< Specify the img scale data format of input and output image. 0: YUV422; 1: YUV420.(obsolete) */
u8 reserved0 : 5;
u8 job_queue_depth; /*!< Specify the depth of scaling task queue inside DSP. */
u8 reserved1[2];
struct iav_window max_input; /*!< Specify max input */
struct iav_window max_output; /*!< Specify max output */
};
struct iav_scale_buf_info {
union {
u32 pid; /*!< Specify memory partition id. Only valid when use_phys = 0 */
int dma_buf_fd;
};
u32 use_phys : 1; /*!< This is a flag to specify if the buffer start address is physcial
address (use_phys = 1) or offset within a memory partition (use_phys = 0). */
u32 use_dma_buf_fd : 1; /*!< This is a flag to specify whether @b dma_buf_fd or @b pid is used. */
u32 reserved : 30;
union {
unsigned long y_offset; /*!< Specify Y buffer offset within the memory partition. Only valid when use_phys = 0 */
unsigned long y_addr; /*!< Specify Y buffer physical address. Only valid when use_phys = 1 */
};
union {
unsigned long uv_offset; /*!< Specify UV buffer offset within the memory partition. Only valid when use_phys = 0 */
unsigned long uv_addr; /*!< Specify UV buffer physical address. Only valid when use_phys = 1 */
};
u16 pitch; /*!< buffer pitch */
u16 height; /*!< buffer height */
};
struct iav_img_scale {
enum iav_yuv_format format; /*!< Input YUV format. When output_format_enable is 0, input and output have same format. */
struct iav_rect input; /*!< input crop window in input_buf domain. */
struct iav_rect output; /*!< output size in output_buf domain. */
struct iav_scale_buf_info input_buf; /*!< input YUV buffer. Y is planar format, UV is interleaved format. */
struct iav_scale_buf_info output_buf; /*!< output YUV buffer. Y is planar format, UV is interleaved format. */
u32 non_block_flag : 1; /*!< non-blocking call flag */
u32 input_skip_cache_sync : 1; /*!< The input buffer cache will not be synced if this flag is enabled. */
u32 output_skip_cache_sync : 1; /*!< The output buffer cache will not be synced if this flag is enabled. */
u32 output_format_enable : 1; /*!< Enable flag of specifing output format.
0: output has same format as input format @ref iav_yuv_format.
1: output has its own format in @ref output_format. */
u32 reserved : 28;
u64 task_id; /*!< Output param: the unique task id of current image scaling task. */
enum iav_yuv_format output_format; /*!< Output format. Only valid when output_format_enable is 1. */
};
struct iav_wait_img_scale {
u64 task_id; /*!< Unique image scaling task id */
};
struct iav_system_resource {
u8 encode_mode; /*!< Encode modes for different cases. @sa dsp_mode.
0x00: Normal ISO mode. This is the mode for lowest latency from VIN to VOUT.
0x01: Multi Region Dewarp mode. This is the mode for multi-region fisheye dewarp.
0x03: Horizon Keeping mode. This is the mode for horizon keeping use cases, only available for CV72 & CV75.
0x04: Multiple Output Fusion mode. This is the mode for RGB and IR output fusion.
0x05: Line interleaved HDR mode. This is the mode for 3X HDR.
0x08: Image Pipeline Only mode. This is the mode for EIS source channel.
0x09: AISP mode. This is the mode to improve Image Quality based on the neural network.
0x0A: Multi Region DPTZ mode. This is the mode for multi-region dptz.
0x7F: Mode none. This is the mode to skip ISP processing for current channel.
0xFF: Current encode mode. This is the mode to get current encode mode number. */
u8 max_stream_num; /*!< The maximum supported stream number in the specified encode mode */
u8 canvas_num; /*!< Canvas number. @sa IAV_MAX_CANVAS_BUF_NUM */
u8 chan_num; /*!< Channel number. @sa IAV_MAX_CHANNEL_NUM */
/* Writable for different configuration */
u32 mixer_a_enable : 1; /*!< This is a flag to enable / disable mixer a */
u32 mixer_b_enable : 1; /*!< This is a flag to enable / disable mixer b */
u32 osd_from_mixer_a : 1; /*!< This is a flag to specify mixer a used for stream overlay */
u32 osd_from_mixer_b : 1; /*!< This is a flag to specify mixer b used for stream overlay */
u32 vsync_detection_disable : 1; /*!< Disable vsync detection or not */
u32 vsync_loss_dummy_frame_enable : 1; /*!< When enabling this flag, DSP will generate and output dummy frames with black PM for the vsync-loss vin. */
u32 me0_scale : 2; /*!< This is a flag to indicate ME0 scale factor, @sa iav_me0_scale */
u32 hevc_off : 1; /*!< Disable HEVC encoding */
u32 chan_vcap_mode_enable : 1; /*!< This is a flag to enable / disable using vcap_mode_flags of each channel. */
u32 enc_raw_rgb : 1; /*!< This is a flag to enable / disable encoding from raw CFA data */
u32 enc_raw_yuv : 1; /*!< This is a flag to enable / disable encoding from raw YUV422 data */
u32 enc_raw_nv12 : 1; /*!< This is a flag to enable / disable encoding from raw YUV420 data */
u32 enable_hp_fps : 1; /*!< This is a flag to enable / disable high precision fps for idsp_fps, canvas, pyramid and stream fps. */
u32 enable_vin_precise_sync : 1; /*!< This is a flag to precisely adjust VIN frame rate according to VOUT frame rate. It's widely used for the cases which require accurate VIN-VOUT sync */
u32 hevc_pjpeg_size_MB_per_tile : 5; /*!< Specify the DRAM size of HEVC PJPEG encoding buffer. */
u32 avc_pjpeg_size_MB_per_tile : 5; /*!< Specify the DRAM size of AVC PJPEG encoding buffer. */
u32 img_statis_zero_copy_enable : 1; /*!< This is a flag to enable / disable image aaa statis zero copy for user app. */
u32 mjpeg_pjpeg_size_MB_per_tile : 5; /*!< Specify the DRAM size of MJPEG PJPEG encoding buffer. */
u32 vin_frame_broken_dummy_repeat : 1; /*!< This is a flag to enable DSP to repeat the last good frame when frame broken is detected. */
u32 chan_map; /*!< This is a bit map to specify channel map. */
u32 canvas_map; /*!< This is a bit map to specify canvas map. */
u32 stream_map; /*!< This is a bit map to specify stream map. */
u32 extra_raw_dram_buf_num : 8; /*!< The number of extra raw dram buffer */
u32 vout_underflow_prevention : 3; /*!<! Specify the value of underflow prevention for VOUT>*/
u32 arb_blend_enable : 1; /*!< This is a flag to enable / disable arbitrary blending. It is recommended for the
scenario where there are channels blended at arbitrary position and orders. At current stage,
this feature is only supported under enc-mode 1.*/
u32 arb_blend_max_areas : 5; /*!< This is to specify the max arbitrary blend area number, only valid when "arb_blend_enable" is 1.*/
u32 overlay_disable : 1; /*!< This is a global flag to enable(0) / disable(1) overlay insertion to the canvas/stream. Default is 0. */
u32 dsp_recover_enable : 1; /*!< This is a flag to enable / disable DSP recovery after DSP assertion. */
u32 enable_vin_idsp_instant_update : 1; /*!< This is a flag to enable / disable VIN and iDSP config being updated instantly inside DSP. */
u32 reserved0 : 12;
u32 vsync_loss_pm_delay : 16; /*!< Specify the vsync loss dummy frame pm cover delay time (ms). Default is 0.*/
u32 reserved1 : 16;
u32 reserved2[7];
/* Debug only */
u32 debug_enable_map; /*!< This is a bit map to specify debug options. @sa iav_debug_type
Bit 0: Enable / Disable debug chip ID option
Bit 1: Enable / Disable debug break point for ISP
Bit 2: Set debug hevc encode mode
Bit 3: Set debug vsync loss timeout time
BIT 4: Set debug maximum chroma radius
BIT 5: Set debug ce off
BIT 6: Enable / Disable debug dsp performance optimal mode
BIT 7: Enable / Disable low delay mode for mode 0
Bit 8: Enable / Disable debug preblend only for aisp mode 9
Bit 9: Set debug max tile num
Bit 10: Set debug group tolerance
Bit 11: Set dsp cmd cache num of overlay and blur per frame time
Bit 12: Set AISP pipe mode
Bit 13: set the heart beat interval of the IAV watchdog */
u32 debug_chip_id : 6; /*!< This is a debug option to specify the debug chip ID */
u32 debug_break_point : 1; /*!< This is a debug flag to specify IK debug point or not. 0: Disable, 1: Enable */
u32 debug_hevc_enc_mode : 3; /*!< This is debug flag to specify HEVC encode mode. */
u32 debug_vsync_loss_timeout : 12; /*!< This is a debug option to specify the vsync loss timeout time (ms).*/
u32 debug_max_chroma_radius : 2; /*!< This is a debug option to specify the maximum chroma radius, @sa iav_chroma_radius_num */
u32 debug_ce_off : 1; /*!< This is a debug option to diable ce */
u32 debug_perf_opt_enable : 1; /*!< This is a debug option to enable or disable dsp performance optimal mode. */
u32 debug_low_delay_enable : 1; /*!< This is a debug option to enable or disable low delay mode for mode 0. */
u32 debug_preblend_only_for_aisp : 1; /*!< This is a debug option to enable preblend pass only for AISP (mode 9).*/
u32 debug_max_slice_num : 4; /*!< This is a debug option to specify the maximum slice num */
struct iav_img_scale_cfg img_scale_cfg; /*!< img scale configuration */
u32 debug_chan_group_tolerance : 8; /*!<! Specify the group sync tolerance value to adapt the eof drift between different sensors within one group */
u32 debug_overlay_blur_cache_cmd_num_minus_2 : 2; /*!<! Specify the dsp cmd cache num of overlay and blur per frame time */
u32 debug_aisp_pipe_mode : 2; /*!<! Specify AISP pipe mode; 0: run AISP low cvflow usage mode; 1: run AISP low latency mode; */
u32 debug_heart_beat_intval_time : 16; /*!< Specify the heart beat interval time for the IAV watchdog, it must be a multiple of 50, unit: ms.
If set to 0, the IAV watchdog will be disabled. */
u32 reserved3 : 4;
u32 reserved4[10]; /*!< Aligned to 128B */
};
struct iav_pass_cfg {
u8 input_pass_id; /*!< Input pass ID for current pass */
u8 input_buf_id; /*!< Input buffer ID for current pass, fixed from Main (0) only */
u8 reserved[2];
};
struct iav_chan_cfg {
u32 chan_id : 8; /*!< Input channel ID */
u32 vsrc_id : 8; /*!< VIN Source ID from which current channel gets the raw data */
u32 img_stats_src_chan : 8; /*!< The source channel ID whose 3A statistic data is used to do 3A control for
current channel. Generally, each channel uses its own 3A statistic data to do 3A control.
While for application cases like multi-channel from single vin or stitching among different
channels, all channels can use the same channel's 3A statistic data to do 3A control. */
u32 sensor_ctrl : 1; /*!< This is a flag to enable / disable setting shutter/agc control to current channel's
VIN Source. When current channel is a virtual channel in multi-channel from single vin case,
need to set this flag to 0. Default is 1. */
u32 enable_group : 1; /*!< Enable channel grouping. The channels in same group must run same frame rate. */
u32 group_sync : 1; /*!< Enable channel grouping synchronization. 0(default): disable; 1: enable */
u32 group_idx : 2; /*!< Group index. Range: 0~3. Only valid when enable_group = 1. */
u32 group_order_idx : 3; /*!< This is the channel order idx inside the group with the group index "group_idx".*/
u32 pass_num : 2; /*!< Total pass num for current channel */
u32 idsp_fps_locked_enable : 1; /*!< Keep channel IDSP fps locked, not changed with VIN frame rate */
u32 vin_roi_idx : 3; /*!< VIN roi index. Only valid when vin roi is enabled. */
u32 c2y_burst_tile : 1; /*!< This is a flag to enable / disable c2y burst tile mode. Default is 1. */
u32 lens_warp_enable : 1; /*!< This is a flag to enable / disable lens warp. It must be enabled if user want to
use LDC function. */
u32 packing_mode_enable : 1; /*!< This is a flag to enable / disable VIN packing mode. Only valid when
raw_capture_enable = 1. */
u32 rotate_cw : 1; /*!< Channel clockwise 90 degree rotation flag; 0: No clockwise rotation of 90;
1: A clockwise rotation of 90. */
u32 hflip : 1; /*!< Channel horizontal flip flag; 0: No horizontal flip; 1: Horizontal flip */
u32 vflip : 1; /*!< Channel vertical flip flag; 0: No vertical flip; 1: Vertical flip */
u32 raw_capture : 1; /*!< Individual raw capture enable flag. */
u32 mctf_cmpr : 1; /*!< This is a flag to enable / disable mctf compression. Default is 1. */
u32 app_img_profile : 5; /*!< The image 3A profile for different scenarios (IPC or Auto),
@sa iav_app_img_profile. */
u32 vsrc_region_num : 4; /*!< The number of regions(line-interleaved) in a single vsrc. */
u32 vsrc_region_map : 4; /*!< The region index map for current channel. */
u32 ext_mem : 1; /*!< This is a flag to enable / disable external memory for raw. */
u32 pre_dec_enable : 1; /*!< This is a flag to specify to decode first to generate YUV, and then feed into IDSP pipeline. */
u32 pre_dec_type : 2; /*!< This is a flag for decoder type, only valid when pre_dec_enable = 1. @sa iav_decoder_type. */
u32 is_post_warp_pm : 1; /*!< This is a flag to enable / disable PM at post warp stage. Enable this for EIS channel. */
u32 raw_manual_feed : 1; /*!< This is a flag to enable / disable channel raw manual feed */
u32 raw_feed_frame_num : 7; /*!< Feed frame num for manual feed, external memory or encode from raw case. It should be set when
@b ext_mem = 1 or @b raw_manual_feed = 1.*/
u32 expo_num : 3; /*!< Exposure number. Valid range is 1~4. By default, IAV driver sets expo_num according to
hdr_mode in struct vindev_mode */
u32 use_vsrc_ctx_pattern : 1; /*!< This is a flag to enable / disable vsrc_ctx pattern mode. */
u32 vsrc_ctx : 4; /*!< Specify the sensor Context ID of vsrc_id for current channel.
For dual-context supported sensors, vsrc_ctx can be set to 1. Else, only 0 is used. */
u32 idsp_fps : 10; /*!< IDSP output FPS. Customers can use this parameter to select a channel FPS lower than
VIN FPS. Default is 0(equals to VIN FPS). */
u32 max_cawarp_h_spacing : 3; /*!< This is an option to specify the max CA Warp horizontal spacing exponent, range from 0 ~ 7, default is 0. */
u32 img_stats_enable_group : 1; /*!< This a flag to enable grouping for 3A control. Channels in the same stats group will apply same 3A control data. */
u32 img_stats_group_idx : 2; /*!< 3A statistic data group index. Range: 0~3. Only valid when img_stats_enable_group = 1. */
u32 max_vwarp_wait_lines : 10; /*!< Specify maximum vwarp wait lines for LDC and fisheye dewarp use case. */
u32 extra_downscale_enable : 1; /*!< Enable extra downscale if downscale >= 6X. Default is 0. */
u32 high_perf_enable : 1; /* !< This is a flag to enable IDSP high performance mode.(obsolete) */
u32 y12_enable : 1; /*!< This is a flag to enable / disable c2y y12 output. */
u32 idsp_core_cfg_enable : 1; /*!< This is a flag to enable / disable customized idsp core mode. */
u32 idsp_core_mode : 2; /*!< Specify idsp core mode, @sa iav_idsp_core_mode. Only valid when idsp_core_cfg_enable = 1. */
u32 extra_iso_cfg : 5; /*!< Extra iso cfg buffer number. It is to enlarge iso cfg ring buffer number. */
u32 srcbuf_to_skip_blend : 8; /*!< This is a flag to skip sub source buffer blend pass in stitching. Main buffer
always has blend pass, it cannot be skipped. It's ONLY available when system is NOT IAV_BLEND_TYPE_NONE.
For example, 2nd srcbuf is to set bit[1], 3rd srcbuf is to set bit[2], ... */
u32 ca_warp_enable : 1; /*!< This is a flag to enable / disable CA Warp function. */
u32 ce_off : 1; /*!< Disable ce for current channel. */
u32 motion_output_enable : 1; /*!< This is a flag to enable / disable motion stream data output function. */
u16 max_padding_width; /*!< The maximum padding width for LDC stitching. It should only be set when @b lens_warp_enable = 1. */
u16 max_main_input_width; /*!< The maximum input width for main buffer. This param needs to be configured when
user application wants to get a small main buffer input size like 720x480 with a large vin size
like 3840x2160. If this param is set, main buffer input width cannot exceed it through run-time
update during Prevew / Encoding state. Default is 0(equals to VIN raw width). */
u16 max_warp_input_width; /*!< The maximum warp input width. It's used when LDC or dewarp functions enabled. */
u16 max_warp_output_width; /*!< The maximum warp output width. It's used when LDC or dewarp functions enabled. Only valid when warp_area_max_cfg_enable = 0. */
u32 max_vwarp_blk_height : 7; /*!< Specify maximum vwarp block height for LDC use case. */
u32 raw_cached_items : 5; /*!< The raw cached items for user to query with blocking call, default: 1. */
u32 y12_cached_items : 5; /*!< The y12 cached items for user to query with blocking call, default: 1. */
u32 vcap_mode_flags : 8; /*!< This is to specify vcap_mode for each channel. Only valid when chan_vcap_mode_enable = 1.
Vcap modes for different cases. @sa dsp_mode.
0x00: Advanced ISO mode. This is the mode for lowest latency from VIN to VOUT.
0x01: Multi Region Dewarp mode. This is the mode for multi-region fisheye dewarp.
0x03: Horizon Keeping mode. This is the mode for horizon keeping use cases, only available for CV72 & CV75.
0x04: Multiple Output Fusion mode. This is the mode for RGB and IR output fusion.
0x05: Line interleaved HDR mode. This is the mode for 3X HDR and multi-pass scale.
0x08: Image Pipeline Only mode. This is the mode for EIS source channel.
0x09: AISP mode. This is the mode to improve Image Quality based on the neural network.
0x0A: Multi Region DPTZ mode. This is the mode for multi-region dptz.
0x7F: Mode none. This is the mode to skip ISP processing for current channel.
0x80: Automatic mode. This is the flag to let vcap_mode_flags follow encode_mode. */
u32 chan_input_src : 3; /*!< This is a flag to set input source for channel. 0: RAW, 1: CE, 2: Low_Res. */
u32 isp_nn_type : 4; /*!< This is to specify the ISP NN type for this channel, default is IAV_ISP_NN_TYPE_NONE. Refer to enum iav_isp_nn_type for different values. */
u32 vsrc_ctx_pattern; /*!< vsrc_ctx pattern. Only valid when use_vsrc_ctx_pattern = 1. */
u32 vsrc_ctx_pattern_mask; /*!< vsrc_ctx pattern mask. Only valid when use_vsrc_ctx_pattern = 1. */
struct iav_pass_cfg pass_cfg[IAV_MAX_PASS_NUM];
struct iav_window buf_max[IAV_MAX_PASS_NUM][IAV_SRCBUF_NUM]; /*!< The maximum resolution (only width is needed)
for source buffers, which is used for allocating line buffers in DSP. It is recommended not
to exceed the sensor resolution. */
u32 input_burst_tile_disable : 1; /*!< This is flag to disable burst tile input for mode 1/mode 3, default : 0. */
u32 warp_vh_only : 1; /*!< This is a flag to declare that multi-region dewarp channel will only have vh pipeline regions. */
u32 min_warp_h_spacing : 3; /*!< Minimum H spacing in mode 3. [0, 6]. @sa iav_warp_params. If 0, iav will calculate according to max_main_input_width / MAX_GRID_WIDTH_HKM. */
u32 warp_padding_width : 10; /*!< The maximum padding width for the 2nd hwarp stage in rotation pipeline or in mode 3. */
u8 blend_left_or_top : 1; /*!< This is a flag to enable / disable left / top channel blend. It's ONLY available when
system is NOT IAV_BLEND_TYPE_NONE. */
u8 blend_right_or_bot : 1; /*!< This is a flag to enable / disable right / bot channel blend. It's ONLY available when
system is NOT IAV_BLEND_TYPE_NONE. */
u32 eis_delay_count : 7; /*!< This is a param to specify EIS delay frame num before IDSP pipeline
for each channel. Valid range is [0, EIS_DELAY_COUNT_MAX]. Default is 0. */
u32 raw_src_chan : 8; /*!< This is a param to specify multi region dewarp or multi output fusion source channel. (obsolete for EIS).*/
u32 idsp_fps_hp; /*!< High precision framerate. idsp_fps_hp = 1000 * idsp_fps. For setting, only valid when "enable_hp_fps" is 1.
For getting, value is always valid. */
/* Below fields are @b Read @b Only parameters */
u32 reserved1 : 5;
u32 is_broken : 1; /*!< This is a flag to show this channel is active or not according to its vin source status.
0(Default): active; 1: is broken. @b Read @b Only. */
u32 hdr_type : 2; /*!< Current Channel's HDR mode. @b Read @b Only. */
u32 amba_img_flow_mode : 4; /*!< This is a flag to show 3A img flow mode. 0: Linear; 1: 2x HDR; 2: 3x HDR;
3: 4x HDR; 15: WDR. @b Read @b Only. */
u32 slice_width : 13; /*!< Current Channel's slice width at Y2Y stage. @b Read @b Only. */
u32 max_chroma_radius : 2; /*!< Maximum chroma radius. @b Read @b Only. @sa iav_chroma_radius_num */
u32 c2y_slice_num : 4; /*!< Current Channel's slice num at C2Y stage. @b Read @b Only. */
u32 reuse_src_chan_iso_cfg : 1; /*!< This is a flag to enable using duplicated 3A configuration of master channel. Only valid when
current channel is idsp virtual channel with sensor_ctrl = 0. Default is 0. */
u32 possible_vsrc_map; /*!< VIN Source ID map to specify which vsrcs are bound to current channel */
u32 raw_slice_num : 8; /*!< This is a flag to set the capture slice num for DSP. */
u32 raw_slice_cached_items : 8; /*!< The raw slice cached items for user to query with blocking call, default: 0. */
u32 raw_width : 16; /*!< Current Channel's raw width. @b Read @b Only. */
u32 raw_height : 16; /*!< Current Channel's raw height. @b Read @b Only.
User can use this two parameters to get actual raw width and height.
For scale/crop VIN, it is scaled/cropped raw size, otherwise it is the original raw size. */
u32 motion_cached_items : 5; /*!< The motion data cached items for user to query with blocking call, default: 0. */
u32 src_from_canvas_enable : 1; /*!< This is a flag to enable channel input from canvas. Only valid when channel is in
DSP_MULTI_REGION_WARP_MODE, DSP_HORIZON_KEEPING_MODE or DSP_MULTI_OUTPUT_FUSION_MODE. */
u32 src_canvas_id : 8; /*!< The canvas id for this channel source. Only valid in DSP_MULTI_REGION_WARP_MODE,
DSP_HORIZON_KEEPING_MODE or DSP_MULTI_OUTPUT_FUSION_MODE mode and src_from_canvas_enable = 1. */
u32 aisp_second_stats_enable : 1; /*!< This is a flag to enable second set of 3A statistic, only valid for AISP. */
u32 sw_ce_enable : 1; /*!< This is a flag to enable / disable software CE for ALTM (Adaptive Local Tone Mapping). */
u32 raw_fps : 16; /*!< RAW frame output FPS from VIN, must be no larger than sensor FPS.
Default is 0 (equal to Sensor FPS). */
u32 ver_slice_num : 2; /*!< This is to specify the IDSP vertical slice number. Default is 1. */
u32 max_chroma_wait_lines : 7; /*!< This is the base wait lines for chroma in mode 0. @b Read @b Only. */
u32 ce_format : 3; /*!< This is a flag to show this channel's ce format. 0(Default): 4H1V;
1: 2H2V; 2: 4H2V; 3: 4H4V. Only valid when ce_format_enable = 1. For getting, value is always valid. */
u32 vin_mo_enable : 1; /*!< This is a flag to enable vin mo.
Only valid when vin_mo_cfg_enable = 1. For getting, value is always valid. */
u32 ce_format_enable : 1; /*!< This is a flag to disable/enable ce_format configurations. Default is 0. */
u32 vin_mo_cfg_enable : 1; /*!< This is a flag to disable/enable customized vin mo cfg. Default is 0. */
u32 warp_area_max_cfg_enable : 1; /*!< This is a flag to disable/enable per area max cfg for multi region dewarp mode. Default is 0 . */
u32 raw_fps_hp; /*!< High precision framerate. raw_fps_hp = 1000 * raw_fps. */
u32 raw_padding_height : 16; /*< This is to specify the padding height of the raw image.
Only valid when ver_slice_num > 1. Default is 0. */
u32 idsp_bypass_enable : 1; /*!< IDSP bypassing enables DSP to encode from YUV buffer. */
u32 min_iso_retire_frames : 8; /*!< Minimum iso cfg retire latency at frames. @b Read @b Only. */
u32 c2y_raw_out_enable : 1; /*!< This is a flag to enable / disable c2y raw out. */
u32 c2y_raw_format : 3; /*!< This is a flag to specify c2y raw format. @sa IAV_C2Y_RAW_FORMAT.
0:Automatically decided by iav, read to get the actual format; 1:8bits. Only valid when c2y_raw_out_enable = 1. */
u32 ir_output_type : 2; /*!< This is an option to specify IR output type. 0 - disabled, 1 - full size, 2 - 1/4 size.
@sa iav_ir_output_type. */
u32 raw_padding_optimize : 1; /*!< This is a flag to enable / disable the optimization of raw padding between adjacent tiles. */
u32 max_raw_width : 16; /*!< This is a option to specify maximum raw width to support dynamic VIN resolution change. */
u32 max_raw_height : 16; /*!< This is a option to specify maximum raw height to support dynamic VIN resolution change. */
u32 debug_max_chroma_radius_enable : 1; /*!< This is a flag to disable/enable maximum chroma radius configurations. */
u32 debug_max_chroma_radius : 3; /*!< Current Channel's max chroma radius. Only valid when debug_max_chroma_radius_enable = 1. */
u32 debug_max_slice_num_enable : 1; /*!< This is a flag to disable/enable maximum slice num configurations. */
u32 debug_max_slice_num : 4; /*!< Current Channel's max slice num. Only valid when debug_max_slice_num_enable = 1. */
u32 debug_low_delay_enable : 1; /*!< This is a flag to disable/enable low delay mode configurations. */
u32 debug_low_delay : 1; /*!< Enable or disable low delay mode of mode 0 for current channel.
Only valid when debug_low_delay_enable = 1. */
u32 debug_dz1_off_enable : 1; /*!< This is a flag to disable/enable DZ-I off configurations. */
u32 debug_dz1_off: 1; /*!< Enable or disable DZ-I for current channel. Only valid when debug_dz1_off_enable = 1 and ce_off = 1. */
u32 debug_slice_cfg_enable : 1; /*!< This is a flag to disable/enable slice related configurations. */
u32 debug_slice_num : 4; /*!< Current Channel's slice num at WARP stage. 0: calculated by IAV automatically.
Only valid when debug_slice_cfg_enable = 1. */
u32 high_mp_arbitrary_zoom_buf_map : 8; /*!< This is the source buffer map for high mega arbitrary zoom.
Only valid for pass 0. */
u32 max_warp_area_num : 4; /*!< The maximum warp areas in channel. This value cannot bigger than MAX_NUM_WARP_AREAS */
u32 idsp_sync_enable : 1; /*!< This is a flag to enable / disable the frame sync operations in idsp. */
u32 reserved2 : 1;
u32 statis_sync_enable : 1; /*!< This is a flag to disable / enable to synchronize 3A statis report after VIN EOF. */
u32 statis_sync_delay_ms : 8; /*!< This is the 3A statis report delay in ms after VIN EOF. Only valid when statis_sync_enable = 1. */
u32 src_buf_hflip_map : 8; /*!< This is the source buffer map to enable horizontal flip function. */
u32 report_pts_info_enable : 1; /*!< This is a flag to disable / enable to report vin pts info to 3A. */
u32 min_hwarp_hspacing_exponent : 3; /*!< Minimal horizontal spacing in hwarp table. Only valid when raw_padding_optimize = 1. */
u32 c2y_raw_cached_items : 5; /*!< The c2y raw cached items for user to query with blocking call, default: 1. */
u32 max_mrd_area_num : 4; /*!< The maximum multi region dptz areas in channel. This value cannot bigger than MAX_NUM_DPTZ_AREAS */
u32 reserved3 : 2;
u16 max_mrd_input_width; /*!< The maximum region input width. It's used in multi region dptz mode. */
u16 max_mrd_output_width; /*!< The maximum region output width. It's used in multi region dptz mode. */
u32 ce_go_map_delay_count : 3; /*!< This is a param to specify CE go map delay frame num between the pass1a and c2y pipeline
for each channel. Valid range is [0, GO_MAP_DELAY_COUNT_MAX]. Default is 0. Only valid when sw_ce_enable = 1. */
u32 deci_raw_cached_items : 5; /*!< The deci raw data cached items for user to query with blocking call, default: 1. */
u32 reserved4 : 24;
u32 reserved5[7]; /*!< Aligned to 256B */
};
struct iav_frame_tag {
u32 value; /*!< Frame tag pattern value. */
u32 mask; /*!< Frame tag pattern mask. */
};
struct iav_canvas_order {
u32 id : 5; /*!< Canvas ID */
u32 valid : 1; /*!< This is a flag to enable / disable Canvas Channel Order. */
u32 chan_num : 5; /*!< The total number of channels whose source buffers are on current Canvas. */
u32 reserved : 21;
u8 chan_order[IAV_MAX_CHANNEL_NUM]; /*!< Channel orders */
};
struct iav_canvas_cfg {
u8 canvas_id; /*!< Input canvas ID */
s8 extra_dram_buf; /*!< The extra dram buffer number for current canvas. Valid range -3~8. */
u16 vout_id : 2; /*!< This is a flag to set VOUT ID. It is valid only when Canvas Type is
IAV_CANVAS_TYPE_PREVIEW or IAV_CANVAS_TYPE_ENCODE_PREVIEW. */
u16 vout_YUV422 : 1; /*!< Specify VOUT YUV data format. 0: YUV420; 1: YUV422. It is valid only when Canvas Type is
IAV_CANVAS_TYPE_PREVIEW. */
u16 manual_feed : 1; /*!< bit flag to control manual feed mode. 1 means using manual feed, 0 means using
internal buffer. */
u16 feed_frame_num : 7; /*!< canvas frame item num for manual feed and and external memory case. */
u16 enc_dummy_latency : 4; /*!< The encode dummy latency buffer number for current Canvas. Valid range 0~15. */
u16 disable_yuv_dram : 1; /*!< This is a flag to allow dsp allocate canvas yuv buffer or not.
0(Default): Allocate buffer; 1: Not allocate buffer. */
u16 set_min_unlocked_buf_num : 1; /*!< bit flag to control whether use min_unlocked_buf_num or not.
0: not set; 1: set. */
u16 enable_frame_tag : 1; /*!< This is a flag to enable / disable frame tag pattern. */
u16 zero_fps : 1; /*!< When zero_fps is 0, "frame_rate = 0" represents idsp_fps. When zero_fps = 1, "frame_rate = 0" is real 0 fps. */
u16 fps_locked_enable : 1; /*!< Keep canvas fps locked. When idsp fps is changed on the fly, it will not be changed proportionally
when it is <= idsp fps.*/
u16 ext_mem : 1; /*!< This is a flag to enable / disable external memory for the canvas. */
u16 blend_stitch_type : 2; /*!< Specify blend type for multi-channel stitching, @sa IAV_BLEND_TYPE */
u16 clear_background : 1; /*!< Clear this canvas memory to blackground color. */
u16 buf_offset_enable : 1; /*!< This is a flag to enable / disable buffer offset in the canvas.
This is only used for the case of single buffer in the canvas. Default is 0. */
u16 blur_enable : 1; /*!< This is a flag to enable / disable blur insertion to the canvas.
This is only for canvases whose type is IAV_CANVAS_TYPE_ENCODE or IAV_CANVAS_TYPE_ENCODE_PREVIEW. Default is 0. */
u16 max_blur_area_num : 6; /*!< Max possible blur areas to insert. Valid range [0, MAX_NUM_BLUR_AREA]. 0 means using default value 8. */
u16 frame_rate; /*!< Frame rate for the canvas containing sub source buffers. */
u32 cached_items : 8; /*!< The cached canvas items for user to query with blocking call, Valid range:
1~extra_dram_buf; Default: 1. */
u32 min_unlocked_buf_num : 8; /*!< Canvas minimum unlocked buf num. When users want to set min_unlocked_buf_num
accordingly, user need enable manual_feed and set_min_unlocked_buf_num first. Meanwhile,
frame_num > min_unlocked_buf_num */
u32 blend_copy_num_minus_1 : 1; /*!< This is a flag to specify the copy sides minus 1 of the blending area.
Only valid when "blend_stitch_type" isn't 0. */
u32 high_mp_arbitrary_zoom_enable : 1; /* This is a flag to enable / disable high mega buffer with arbitrary zoom. Default is 0. */
u32 alpha_match_table_enable : 1; /* This is a flag to enable / disable match table for overlap areas used by multi-channel stitching. Default is 0. */
u32 blend_warp_enable : 1; /*!< This is a flag to enable / disable H warp for blending overlap region. Only valid when "blend_stitch_type" isn't 0. */
u32 disable_me_dram : 1; /*!< This is a flag to allocate canvas ME buffer or not, 0 means no canvas ME buffer. */
u32 enc_extra_padding_enable : 1; /*!< This is a flag to enable / disable extra padding for stream encoding. */
u32 hevc_width_align_enable : 1; /*!< This is a flag to enable / disable canvas width alignment to improve HEVC encoding efficiency. */
u32 low_delay_enable : 1; /*!< This is a flag to enable / disable canvas low delay output with
multiple IDSP vertical slices enabled (ver_slice_num > 1). Default is 0.*/
u32 vout_virt_chan_id : 3; /*!< VOUT virtual channel ID */
u32 vout_back_pressure_margin : 4; /*!< Specify IDSP VOUT back pressure margin. Default is 0. */
u32 enc_extra_padding_left_enable : 1; /*!< This is a flag to enable / disable extra padding on the left for stream encoding.
It is normally used when stream horizontal flip is enabled. */
enum iav_canvas_type type; /*!< Canvas Type, @sa iav_canvas_type */
struct iav_window max; /*!< Canvas width and height */
struct iav_frame_tag frame_tag; /*!< Canvas frame tag pattern. When the frame's RAW frame tag matches this canvas frame tag pattern value,
this frame data would be written into this canvas. Otherwise, this frame data would be skipped for this
canvas. Only valid when enable_frame_tag = 1 and iav_system_source.enabled_canvas_frame_tag = 1. */
u32 frame_rate_hp; /*!< High precision framerate. frame_rate_hp = 1000 * frame_rate. For setting, only valid when "enable_hp_fps" is 1.
For getting, value is always valid. */
u32 blend_stitch_circular_margin : 10; /*!< The overlap margin of the last channel and first channel. Only valid when "blend_stitch_type" isn't 0. */
u32 motion_output_enable : 1; /*!< This is a flag to enable motion output, valid only in mode 0 and mode 5 */
u32 src_buf_align_type_enable : 1; /*!< This is a flag to enable / disable source buffer align type. Default is 0. Only valid for cv5/cv52. */
u32 src_buf_align_type : 3; /*!< source buffer align type. 0(default): align to 64; 1: align to 128; 2: align to 256; 3: align to 512.
only valid when src_buf_align_type_enable = 1. */
u16 smooth_blur_enable : 1; /*!< This is a flag to enable / disable smooth blur insertion to the canvas.
This is only for canvases whose type is IAV_CANVAS_TYPE_ENCODE or IAV_CANVAS_TYPE_ENCODE_PREVIEW.
It can be used to remove non-useful high frequency details for YUV data(more smooth), default is 0.
when it is enabled, blur_enable will be enabled by default. */
u32 data_report_after_postp: 1; /*!< This is a flag to enable report canvas data after postp. YUV, ME0, and ME1 data of this
canvas will be reported after postp when it is enabled, this means when query this canvas, there may be
overlay, blur (if they are inserted) on the canvas data. */
u32 back_pressure_enable : 1; /* This is a flag to enable canvas back pressure between DSP and ARM.
DSP won't overwrite the canvas frame before ARM releases it manually.
It is only valid for EFR and decoder cases. */
u32 enc_extra_padding_top_enable : 1; /*!< This is a flag to enable / disable extra padding on the top for stream encoding.
It is normally used when stream vertical flip is enabled. */
u32 reserved0 : 13;
struct iav_canvas_order order; /*!< Canvas Channel Order, @sa iav_canvas_order */
u16 extra_width; /*!< Canvas window extra width, only used for multiple output fusion mode. */
u16 extra_height; /*!< Canvas window extra height, only used for multiple output fusion mode. */
u32 debug_postp_hsk_intvl_enable : 1; /*!< This is a flag to enable / disable frame number interval configurations for post-processing (blur/overlay/yuv_remap) buffer handshake.
When this option is disabled, the default interval value 2 is used. */
u32 debug_postp_hsk_intvl : 4; /*!< The frame number intervals for post-processing buffers. Only valid when "debug_postp_hsk_intvl_enable" is enabled.
Valid range 0~7. 0: disable handshake; 1~7: handshake every n cmds. */
u32 reserved1 : 27;
u32 reserved2[7]; /*!< Aligned to 96B */
};
#define PYRAMID_ROI_OFFSET_ALIGN (2) /*!< 2, pyramid crop window x_offset and y_offset alignment */
#define PYRAMID_ROI_HEIGHT_ALIGN (2) /*!< 2, pyramid crop window height alignment */
#define PYRAMID_ROI_WIDTH_ALIGN (2) /*!< 2, pyramid crop window width alignment */
#define PYRAMID_ROI_HEIGHT_ALIGN (2) /*!< 2, pyramid crop window height alignment */
#define PYRAMID_RESCALE_WIDTH_MIN (128) /*!< 128, minimum width of pyramid rescale window, only valid for arbitrary pyramid */
#define PYRAMID_RESCALE_HEIGHT_MIN (64) /*!< 64, minimum height of pyramid rescale window, only valid for arbitrary pyramid */
struct iav_pyramid_cfg {
u32 chan_id : 6; /*!< Input channel ID */
u32 enable : 1; /*!< This is a flag to specify if the pyramid is enabled */
u32 input_buf_id : 3; /*!< Input source buffer ID */
u32 layers_map : 7; /*!< bit map for pyramid layers, one bit for one layer */
u32 manual_feed : 1; /*!< bit flag to control manual feed mode. 1 means using manual feed,
0 means using internal buffer. */
u32 set_min_unlocked_buf_num : 1; /*!< bit flag to control whether use min_unlocked_buf_num or not.
0: not set; 1: set. */
u32 item_num : 8; /*!< pyramid buffer item num for manual feed and external memory case. */
u32 enable_frame_tag : 1; /*!< This is a flag to enable / disable frame tag pattern. */
u32 fps_locked_enable : 1; /*!< Keep pyramid fps locked. When idsp fps is changed on the fly, it will not be changed proportionally
when it is <= idsp fps.*/
u32 reserved0 : 3;
enum iav_pyramid_scale scale_type; /*!< pyramid scale type, @sa iav_pyramid_scale */
u8 frame_rate; /*!< Frame rate for the pyramid output layers. */
u8 min_unlocked_buf_num; /*!< Pyramid minimum unlocked buf num. When users want to set min_unlocked_buf_num
accordingly, user need enable manual_feed and set_min_unlocked_buf_num first. Meanwhile,
item_num > min_unlocked_buf_num */
u16 max_layers_map : 7; /*!< Max bit map for pyramid layers, one bit for one layer, can only be changed before preview. layers_map
should be within max_layers_map. */
u16 cached_items : 6; /*!< The pyramid cached items for user to query with blocking call, default: 1. */
u16 ext_mem : 1; /*!< This is a flag to enable / disable external memory for the pyramid. */
u16 reserved1 : 2;
struct iav_rect crop_win[IAV_MAX_PYRAMID_LAYERS]; /*!< Cropping window in each layer output coordinate */
struct iav_window rescale_size; /*!< Rescale size for pyramid layer 1. The scale factor of W or H
(layer0 -> layer1) must be in the range of <b>1X to 1/8X (Downscale)</b>, while the
scale factor from layerN (1<= N < 6) to layerN+1 is fixed 2X (Downscale) in both width & height.
Only valid when <b>"scale_type == IAV_PYRAMID_SCALE_ARBITRARY"</b>. */
struct iav_window max_rescale_size; /*!< Max rescale size for pyramid layer 1. Used to set the max rescale size of pyramid layer 1,
rescale_size should be within max_scale_size. Only valid when <b>"scale_type == IAV_PYRAMID_SCALE_ARBITRARY"</b>. */
struct iav_frame_tag frame_tag; /*!< Pyramid frame tag pattern. When the frame's RAW frame tag matches this pyramid frame tag pattern value,
this frame data would be written into this pyramid. Otherwise, this frame data would be skipped for this pyramid.
Only valid when enable_frame_tag = 1 and iav_system_source.enabled_canvas_frame_tag = 1.*/
u32 frame_rate_hp; /*!< High precision framerate. frame_rate_hp = 1000 * frame_rate. For setting, only valid when "enable_hp_fps" is 1.
For getting, value is always valid. */
u32 canvas_out_enable : 1; /*!< Enable the output canvas. */
u32 canvas_out_id : 8; /*!< The output canvas ID where the pyramid layers are written into. */
u32 reserved2 : 23;
u32 reserved3[9]; /*!< Aligned to 192B */
};
struct iav_stream_resource {
u32 stream_id : 6; /*!< Input stream ID */
u32 max_M : 3; /*!< The maximum GOP M for each streams. Streams will have B frames when M > 1.
Stream A can have larger range of M from 1 to 3, while the other streams are limited to 1. */
u32 fast_seek_enable : 1; /*!< Fast seek enable flag for each stream. */
u32 two_ref_enable : 1; /*!< Two ref enable flag for each stream. */
u32 max_svct_layers_minus_1 : 2;/*!< This is a flag to specify the value for the maximum SVCT layers minus 1. */
u32 max_num_minus_1_ltrs : 1; /*!< Maximum long term number minus 1 for stream */
u32 codec_enable : 3; /*!< Stream codec configuration @sa iav_codec_option */
u32 stream_mv_statis_enable : 1;/*!< This is a flag to enable MV(motion vector) dump for each stream. */
u32 efm_enable : 1; /*!< This is a flag to enable / disable encoding from memory */
u32 efm_buf_num : 4; /*!< The efm buffer number in one efm buffer pool and only used when efm_enable is 1 */
u32 efm_skip_waiting : 1; /*!< The efm_skip_waiting skip waiting for encoding start/stop status when
it's value is 1 and only used when efm_enable is 1 */
u32 stream_pic_statis_enable : 1;/*!< This is a flag to enable picture statistic dump for each stream. */
u32 efm_extern_src_enable : 1; /*!< Enable to use EFM buffer of other streams' */
u32 efm_extern_src_stream : 6; /*!< Specify stream ID of shared EFM buffer */
u32 enc_core_cfg_enable : 1; /*!< This is a flag to enable / disable customized encoder core mode. */
u32 enc_core_mode : 2; /*!< Specify encoder core mode, @sa iav_enc_core_mode.
Only valid when enc_core_cfg_enable = 1. */
u32 efm_ext_mem : 1; /*!< This is a flag to enable user managed EFM frame buffer */
u32 hevc_width_align_enable : 1; /* This is a flag to enable / disable HEVC width alignment to improve encoding efficiency. */
u32 custom_sei_possible : 1; /*!< This is a flag to alloc custom sei buffer queue for the current stream. */
u32 efm_blur_enable : 1; /*!< This is a flag to enable / disable blur insertion to the EFM stream. */
u32 efm_max_blur_area_num : 6; /*!< Max possible blur areas to insert. Valid range [0, MAX_NUM_BLUR_AREA]. 0 means using default value 8. */
u32 efm_me_idx_enable : 1; /*!< This is a flag to specify YUV and ME index separately for EFM.
This is normally for advanced stream GOPs, and single EFM for multiple streams. */
u32 overlay_pixel_format : 5; /*!< Specify the pixel formal for the stream overlay, see @sa iav_overlay_format_t for details. */
u32 hevc_res_opt_enable : 1; /*!< This is a flag to enable / disable DSP internal resource optimization for HEVC;
0 (default) : potentially better HEVC performance with more DSP internal resource for HEVC;
1 : optimized DSP internal resource for HEVC.*/
u32 quick_state_switch : 1; /*!< This is a flag to enable / disable quick encode state switch for stream start / stop operation. */
u32 reserved0 : 11;
u32 possible_enc_src_map; /*!< This is to specify the possible encoding source canvas map for a stream. */
struct iav_window max_size; /*!< The maximum resolution for encode streams, which is used for allocating memory in
DSP. It is recommended not to exceed the main source buffer resolution. */
struct iav_window efm_size; /*!< The efm buffer size and only used when efm_enable is 1. */
u32 custom_sei_buf_num : 8; /*!< The custom sei buffer number in one stream custom sei buffer pool and
only used when custom_sei_possible is 1. */
u32 custom_sei_data_max_size : 16; /*!< The maximum data size for custom sei, which is used for allocating memory in DSP and iav driver. */
u32 reserved1 : 8;
u32 init_enc_src_map; /*!< This is to specify the stream's initial source canvas map when entering preview state,
and this source canvas map can only include one canvas. */
u32 reserved2[7]; /*!< Aligned to 64B */
};
struct iav_buf_cfg {
struct iav_rect input; /*!< Source Buffer input offset and size */
struct iav_rect output; /*!< Source Buffer output offset and size */
u32 canvas_id : 8; /*!< Canvas ID */
u32 src_buf_hflip : 1; /*!< Source buffer horizontal flip */
u32 reserved : 23;
};
struct iav_dptz {
u8 channel_id; /*!< Channel ID */
u8 pass_id; /*!< Pass ID */
u8 buf_id; /*!< Source Buffer ID */
u8 reserved;
struct iav_buf_cfg buf_cfg; /*!< Source Buffer configuration */
};
struct iav_canvas_fps {
u32 id : 5; /*!< Canvas ID */
u32 zero_fps : 1; /*!< When zero_fps is 0, "frame_rate = 0" represents idsp_fps. When zero_fps = 1, "frame_rate = 0" is real 0 fps. */
u32 reserved : 26;
u32 frame_rate; /*!< Canvas frame rate */
u32 frame_rate_hp; /*!< High precision framerate. frame_rate_hp = 1000 * frame_rate. For setting, only valid when "enable_hp_fps" is 1.
For getting, value is always valid. */
};
struct iav_pyramid_fps {
u32 chan_id : 8; /*!< Channel ID */
u32 reserved : 24;
u32 frame_rate; /*!< Pyramid frame rate */
u32 frame_rate_hp; /*!< High precision framerate. frame_rate_hp = 1000 * frame_rate. For setting, only valid when "enable_hp_fps" is 1.
For getting, value is always valid. */
};
struct iav_mem_cfg_chan {
u32 mask_possible : 1; /*!< Whether Single-Color Privacy Mask memory is needed. */
u32 warp_possible : 1; /*!< Whether WARP memory is needed for Dewarp/EIS/LDC. */
u32 mask_buf_max_num : 6; /*!< Max allocated Single-Color PM buffer num. 1 for user configuration, others
for IAV/DSP usage. */
u32 warp_buf_max_num : 6; /*!< Max allocated WARP buffer num. 1 for user configuration, others for IAV/DSP
usage. */
u32 warp_area_max_num : 6; /*!< Max WARP area num. 1 for LDC/EIS, Dewarp can be up to 12. */
u32 rpt_possible : 1; /*!< Whether RPT memory is needed. */
u32 reserved0 : 11;
u32 reserved1;
struct iav_window max_vin; /*!< Max VIN size to decide the buffer allocation. */
};
struct iav_mem_cfg_stream {
u32 qpm_possible : 1; /*!< Whether QP matrix memory is needed. */
u32 qpm_max_matrix_num : 3; /*!< Max QP matrix num per stream. 1: I/P share the same QP matrix;
2: I use 1 QP matrix and P use the other one, max is 3. */
u32 qpm_buf_max_num : 4; /*!< Max allocated QP matrix buffer num. 1 for user configuration, others for IAV/DSP usage. */
u32 reserved : 8;
u32 bsb_size_kb : 16; /*!< This is to specify the BSB buffer size for each stream.
It is only valid in individual BSB buffer mode with DSP_INDIV_BSB_SIZE being specified. */
struct iav_window max_stream; /*!< Max stream size to decide the buffer allocation. */
};
struct iav_mem_layout_resource {
u32 max_chan_num : 5; /*!< Max possible channel num for resource memory allocation. */
u32 max_stream_num : 5; /*!< Max possible stream num for resource memory allocation. */
u32 reserved : 22;
struct iav_mem_cfg_chan chan_mem_cfg[IAV_MAX_CHANNEL_NUM]; /*!< Channel memory configuration */
struct iav_mem_cfg_stream stream_mem_cfg[IAV_STREAM_MAX_NUM_ALL]; /*!< Stream memory configuration */
};
struct iav_mem_layout {
u32 offset; /*!< Memory offset. */
u32 size; /*!< Memory size. */
u32 unit_size; /*!< Buffer unit size. */
u32 unit_num : 8; /*!< Buffer unit number. */
u32 reserved0 : 24;
};
struct iav_mem_layout_chan {
unsigned long phys_base; /*!< Physical memory base address. */
u32 total_user_size; /*!< Total memory size for user configuration. */
u32 total_size; /*!< Total memory size. */
struct iav_mem_layout buf_layout[IAV_MAX_CHANNEL_NUM]; /*!< Buffer layout info. */
};
struct iav_mem_layout_stream {
unsigned long phys_base; /*!< Physical memory base address. */
u32 total_user_size; /*!< Total memory size for user configuration. */
u32 total_size; /*!< Total memory size. */
struct iav_mem_layout buf_layout[IAV_STREAM_MAX_NUM_ALL]; /*!< Buffer layout info. */
};
struct iav_mem_layout_canvas {
unsigned long phys_base; /*!< Physical memory base address. */
u32 total_user_size; /*!< Total memory size for user configuration. */
u32 total_size; /*!< Total memory size. */
struct iav_mem_layout buf_layout[IAV_MAX_CANVAS_BUF_NUM]; /*!< Buffer layout info. */
};
struct iav_mem_layout_raw_pool {
unsigned long phys_base; /*!< Physical memory base address. */
u32 total_user_size; /*!< Total memory size for user configuration. */
u32 total_size; /*!< Total memory size. */
struct iav_mem_layout buf_layout[IAV_MAX_REAL_VIN_NUM]; /*!< Buffer layout info. */
};
struct iav_mem_layout_info {
u32 mem_layout_updated : 1; /*!< Whether resource memory layout updated or not. */
u32 reserved : 31;
struct iav_mem_layout_chan mask_layout; /*!< Single Color Privacy Mask memory layout. */
struct iav_mem_layout_chan warp_layout; /*!< WARP memory layout. */
struct iav_mem_layout_stream qpm_layout; /*!< QP matrix memory layout. */
struct iav_mem_layout_raw_pool raw_pool_layout; /*!< RAW pool memory layout. */
struct iav_mem_layout_canvas canvas_pool_layout; /*!< Canvas pool memory layout. */
struct iav_mem_layout_chan rpt_layout; /*!< RPT memory layout. */
};
struct iav_enc_mode_cap {
u8 encode_mode; /*!< Encode modes for different cases */
u8 max_streams_num; /*!< Maximum supported stream number */
u8 reserved0[2];
u32 max_encode_MB; /*!< The maximum encode macro blocks for all codec,
including H.264/H.265/JPEG*/
u32 max_h26x_encode_MB; /*!< The maximum encode macro blocks for H.264/H.265 codec */
u32 raw_cap_possible : 1; /*!< Possibility to enable raw picture capture */
u32 lens_warp_possible : 1; /*!< Possibility to support lens warp */
u32 iso_type_possible : 3; /*!< Possibility of supported ISO types */
u32 enc_raw_rgb_possible : 1; /*!< Possibility to support encode from raw CFA data input
function. It's not available and it's for internal debug only. */
u32 high_mp_possible : 1; /*!< Possibility to support high mega pixels encoding */
u32 linear_possible : 1; /*!< Possibility to support sensor Linear mode */
u32 hdr_2x_possible : 2; /*!< Possibility of support HDR 2X types */
u32 hdr_3x_possible : 2; /*!< Possibility of support HDR 3X types */
u32 wcr_possible : 1; /*!< Possibility to support wide chroma noise filter */
u32 me0_possible : 2; /*!< Possibility to support ME0 scale factor */
u32 enc_from_mem_possible : 1; /*!< Possibility to support encode from memory */
u32 enc_raw_yuv_possible : 1; /*!< Possibility to support encode from raw YUV data input
function. It's not available and it's for internal debug only. */
u32 ce_possible : 1; /*!< Possibility to support CE function */
u32 stitch_hor_possible : 1; /*!< Possibility to support horizontal stitching. */
u32 stitch_ver_possible : 1; /*!< Possibility to support vertical stitching. */
u32 eis_delay_cnt_possible : 1; /*!< Possibility to support eis delay. */
u32 dvr_possible : 1; /*!< Possibility to support digital video recording. */
u32 vwarp_wait_lines_possible : 1; /*!< Possibility to support vwarp wait lines. */
u32 multi_pass_possible : 1; /*!< Possibility to support multiple scaler pass. */
u32 chan_rotate_possible : 1; /*!< Possibility to support channel rotation and flip. */
u32 multi_yuv_input_possible : 1; /*!< Possibility to support multiple YUV inputs. */
u32 canvas_manual_feed_possible : 1; /*!< Possibility to support canvas manual feed. */
u32 raw_manual_feed_possible : 1; /*!< Possibility to support channel raw manual feed. */
u32 reserved_possible : 4;
struct iav_window min_main; /*!< The min resolution for main buffer */
struct iav_window max_main; /*!< The max resolution for main buffer */
struct iav_window min_enc; /*!< The min resolution for encoding */
};
struct iav_enc_buf_cap {
u8 buf_id; /*!< @sa iav_srcbuf_id */
u8 pass_id; /*!< Pass ID */
u8 reserved0[2];
struct iav_window max; /*!< The maximum resolution of the buffer */
u16 max_zoom_in_factor; /*!< Maximum supported zoom in factor */
u16 max_zoom_out_factor; /*!< Maximum supported zoom out factor */
u16 max_stitch_zoom_out_factor; /*!< Maximum supported zoom out factor for stitched case */
u16 reserved1;
};
struct iav_pyramid_roi {
u32 chan_id : 8; /*!< Channel ID */
u32 layers_map : 7; /*!< Pyramid layer bit map */
u32 reserved0 : 17;
struct iav_rect crop_win[IAV_MAX_PYRAMID_LAYERS]; /*!< crop window */
struct iav_window rescale_size;
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum iav_mem_part_id {
IAV_PART_DSP = 0, /*!< 0, Partition ID for DSP partition */
IAV_PART_BSB = 1, /*!< 1, Partition ID for bit stream partition */
IAV_PART_USR = 2, /*!< 2, Partition ID for user data partition */
IAV_PART_MV = 3, /*!< 3, Partition ID for motion vector partition */
IAV_PART_OVERLAY = 4, /*!< 4, Partition ID for overlay partition */
IAV_PART_QPMATRIX = 5, /*!< 5, Partition ID for QP ROI matrix partition */
IAV_PART_WARP = 6, /*!< 6, Partition ID for warp vector partition */
IAV_PART_QUANT = 7, /*!< 7, Partition ID for JPEG quant matrix table partition */
IAV_PART_IMG = 8, /*!< 8, Partition ID for image partition */
IAV_PART_MASK = 9, /*!< 9, Partition ID for single color mask partition */
IAV_PART_FB_DATA = 10, /*!< 10, Partition ID for fast boot data partition */
IAV_PART_FB_AUDIO = 11, /*!< 11, Partition ID for fast boot audio partition */
IAV_PART_INTRA_PB = 12, /*!< 12, Partition ID for INTRA PB partition */
IAV_PART_STAT = 13, /*!< 13, Partition ID for picture statistics */
IAV_PART_BSH = 14, /*!< 14, for internal use */
IAV_PART_DSP_DEF_CMD = 15, /*!< 15, for internal use */
IAV_PART_DSP_UCODE = 16, /*!< 16, Partition ID for UCODE partition */
IAV_PART_DSP_LOG = 17, /*!< 17, for internal use */
IAV_PART_DSP_FIFO = 18, /*!< 18, for internal use */
IAV_PART_DSP_RSV = 19, /*!< 19, for internal use */
IAV_PART_IAV_RSV = 20, /*!< 20, for internal use */
IAV_PART_PREALLOC = 21, /*!< 21, for internal use */
IAV_PART_PREALLOC2 = 22, /*!< 22, for internal use */
IAV_PART_PYRAMID_POOL = 23, /*!< 23, Partition ID for Pyramid buffer pool in Pyramid manual-feed mode or in decode mode */
IAV_PART_QPMATRIX_RAW = 24, /*!< 24, Partition ID for QPMATRIX_RAW partition */
IAV_PART_CANVAS_POOL = 25, /*!< 25, Partition ID for canvas buffer pool in manual-feed mode */
IAV_PART_INT_BSB = 26, /*!< 26, Partition ID for internal used bit stream partition */
IAV_PART_EXTRA_RAW = 27, /*!< 27, Partition ID for extra raw partition */
IAV_PART_RAW_POOL = 28, /*!< 28, Partition ID for raw buffer pool in raw manual-feed mode */
IAV_PART_H26X_SCALELIST = 29, /*!< 29, Partition ID for AVC/HEVC scalelist partition */
IAV_PART_BLUR = 30, /*!< 30, Partition ID for blur partition */
IAV_PART_ARB_BLUR = 31, /*!< 31, Partition ID for custom blur partition */
IAV_PART_BLEND_ALPHA = 32, /*!< 32, Partition ID for blend alpha buffer */
IAV_PART_MULTI_COLOR_MASK = 33, /*!< 33, Partition ID for Multi Color Mask partition */
IAV_PART_TFC = 34, /*!< 34, Partition ID for TML fusion clut partition */
IAV_PART_VOUT0_FB = 35, /*!< 35, VOUT0 frame buffer partition (obsolete) */
IAV_PART_VOUT1_FB = 36, /*!< 36, VOUT1 frame buffer partition (obsolete) */
IAV_PART_VOUT2_FB = 37, /*!< 37, VOUT2 Frame buffer partition (obsolete) */
IAV_PART_AISP = 38, /*!< 38, Partition ID for Ambarella AISP, used in mode 9 */
IAV_PART_DEC_BSB = 39, /*!< 39, Decoder BSB buffer partition */
IAV_PART_DSP_CV = 40, /*!< 40, Partition ID for DSP and CV internal share, used in mode 9 */
IAV_PART_IMG_STATIS = 41, /*!< 41, Partition ID for image AAA statis when img_statis_zero_copy_enable is enabled */
IAV_PART_BLEND_WARP = 42, /*!< 42, Partition ID for blend warp buffer */
IAV_PART_IMG_NN = 43, /*!< 43, Partition ID for image NN buffer */
IAV_PART_CUSTOM_SEI = 44, /*!< 44, Partition ID for custom sei buffer */
IAV_PART_YUV_REMAP = 45, /*!< 45, Partition ID for yuv remap partition */
IAV_PART_CANVAS_OVERLAY = 46, /*!< 46, Partition ID for canvas overlay partition */
IAV_PART_ARB_BLEND_ALPHA = 47, /*!< 47, Partition ID for arbitrary blend alpha table */
IAV_PART_FUSION = 48, /*!< 48, Partition ID for multiple output fusion CLUT buffer */
IAV_PART_RPT = 49, /*!< 49, Partition ID for raw padding table */
IAV_PART_SMOOTH_BLUR = 50, /*!< 50, Partition ID for smooth_blur partition */
IAV_PART_ARB_SMOOTH_BLUR = 51, /*!< 51, Partition ID for custom smooth blur partition */
IAV_PART_RTOS_IMG = 52, /*!< 52, Partition ID for RTOS image reserved partition */
IAV_PART_CE_GO_MAP = 53, /*!< 53, Partition ID for CE gain and offset map partition */
IAV_PART_NUM = 54, /*!< 54, total number of memory partition */
IAV_PART_FIRST = IAV_PART_DSP, /*!< IAV_PART_DSP */
IAV_PART_LAST = IAV_PART_NUM, /*!< IAV_PART_NUM */
IAV_PART_USR_CUSTOM_ID_FIRST = 192, /*!< 192, First customer ID for user memory partition */
IAV_PART_USR_CUSTOM_ID_LAST = 255, /*!< 255, Last customer ID for user memory partition */
};
enum iav_sync_cache_mem_part_opt {
IAV_CACHE_CLEAN = 0, /*!< Flush data from cache to physical memory.*/
IAV_CACHE_INVALIDATE, /*!< Discard cache data in order to let it reload data from memory.*/
};
enum iav_mem_id {
IAV_MEM_PARTITION = 0x00, /*!< 0x00 */
IAV_MEM_CANVAS = 0x01, /*!< 0x01 */
IAV_MEM_IMG_FIFO = 0x02, /*!< 0x02 */
IAV_MEM_NUM = 0x03, /*!< 0x03 */
};
enum iav_mem_part_acs {
IAV_MEM_PART_ACS_ARM = 0x01, /*!< Bit 0 : (1 << 0) */
IAV_MEM_PART_ACS_VPU = 0x02, /*!< Bit 1 : (1 << 1) */
IAV_MEM_PART_ACS_DSP = 0x04, /*!< Bit 2 : (1 << 2) */
IAV_MEM_PART_ACS_ALL = IAV_MEM_PART_ACS_ARM | IAV_MEM_PART_ACS_VPU | IAV_MEM_PART_ACS_DSP, /*!< 0x07 */
};
/*! @} */ /*End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_mem_info {
unsigned long addr; /*!< Start address of memory partition */
unsigned long length; /*!< Size of the memory partition. */
unsigned long offset; /*!< Offset related to start address. */
};
struct iav_mem_part_info {
u32 pid; /*!< Memory partiton item ID, @sa iav_mem_part_id */
struct iav_mem_info mem; /*!< Memory partition description. */
u32 from_private : 1; /*!< This flag shows the memory pool of this partition memory. 0: IAV shared pool; 1: IAV private pool. */
u32 accessibility : 8; /*!< This param shows the accessibility of this pid partition memory.
Refer to @sa iav_mem_part_acs for different accessibility type. */
u32 reserved0 : 23;
};
struct iav_alloc_mem_part {
u32 pid; /*!< The IAV/DSP sub-partition ID to be allocated, @sa iav_mem_part_id.
For anonymous memory partition allocation, pid is the output parameter
and an unique ID that represents this allocated memory partition. */
u32 enable_cache : 1; /*!< This flag enables or disables the cache when the memory partition is mapped to the user space. */
u32 from_private : 1; /*!< This flag specifies the memory pool for this memory allocation, 0: IAV shared pool; 1: IAV private pool. */
u32 accessibility : 8; /*!< This param specifies the accessibility for this partition memory.
Refer to @sa iav_mem_part_acs for different accessibility type. It will decide which memory pool will be used
to allocate the partition memory. When it is specified, the flag: from_private will be ignored. */
u32 reserved0 : 22;
unsigned long length; /*!< As input: the mem part size to be allocated.
As output: the real size of the allocated mem part. */
unsigned long offset; /*!< the physical address of the allocated mem part. */
};
struct iav_anon_mem_part {
u32 pid; /*< Anonymous pid for register / unregister. */
};
struct iav_alloc_mem_part_fd {
u32 enable_cache : 1; /*!< This flag enables or disables the cache when the memory partition is mapped to the user space. */
u32 from_private : 1; /*!< This flag specifies the memory pool for this memory allocation, 0: IAV shared pool; 1: IAV private pool. */
u32 accessibility : 8; /*!< This param specifies the accessibility for this pid partition memory.
Refer to @sa iav_mem_part_acs for different accessibility type. It will decide which memory pool will be used
to allocate the partition memory. When it is specified, the flag: from_private will be ignored. */
u32 reserved0 : 22;
unsigned long length; /*!< the mem part size to be allocated. */
int dma_buf_fd; /*!< Output param: dma-buf:fd of this memory partition. */
};
struct iav_free_mem_part {
u32 pid; /*!< The mem part to be freed, @sa iav_mem_part_id */
};
struct iav_chan_vsrc_update {
u32 chan_id : 8; /*!< Specifies the channel ID which will bind to a new vin source. */
u32 vsrc_id : 8; /*!< Specifies the new vin source ID which is bound to the specified channel ID. */
u32 skip_idsp_cfg : 1; /*!< Specifies the ignore idsp config flag for current channel. */
u32 reserved0 : 15;
u32 reserved1[7]; /*!< Aligned to 32 Bytes */
};
struct iav_feed_raw {
u8 chan_id; /*!< Specifies the channel ID that needs to feed the raw buffer. */
u8 reserved0[3];
};
struct iav_feed_pyramid {
u8 chan_id; /*!< Specifies the channel ID that needs to feed the pyramid buffer. */
u8 reserved0[3];
};
struct iav_feed_canvas {
u8 canvas_id; /*!< Specifies the canvas ID that needs to feed the canvas buffer. */
u8 reserved0[3];
};
struct iav_mem_canvas_info {
u32 id_map; /*!< The canvas id map for the queried canvases' memory blocks. */
struct iav_mem_info yuv[IAV_MAX_CANVAS_BUF_NUM]; /*!< The memory partition information of YUV buffer. */
struct iav_mem_info me[IAV_MAX_CANVAS_BUF_NUM]; /*!< The memory partition information of ME buffer. */
};
struct iav_sync_cache_mem_part {
u32 pid; /*!< mem part buf id. */
enum iav_sync_cache_mem_part_opt opt; /*!< sync operation: invalidate or clean. */
unsigned long offset; /*!< mem part buf address offset. */
unsigned long length; /*!< mem part buf length. */
};
struct iav_mem_img_fifo_info {
u32 chan_num : 4; /*!< The total number of channels. */
u32 reserved : 28;
struct iav_mem_info vin_fifo[IAV_MAX_CHANNEL_NUM]; /*!< The VIN statistics FIFO memory info. */
struct iav_mem_info rgb_fifo[IAV_MAX_CHANNEL_NUM]; /*!< The RGB statistics FIFO memory info. */
struct iav_mem_info cfa_fifo[IAV_MAX_CHANNEL_NUM]; /*!< The CFA statistics FIFO memory info. */
};
struct iav_querymem {
enum iav_mem_id mid; /*!< Query memory block item ID, @sa iav_mem_id */
union {
struct iav_mem_part_info partition;
struct iav_mem_canvas_info canvas;
struct iav_mem_img_fifo_info img_fifo;
} arg;
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper */
#define IAV_GDMA_MAX_WIDTH (4096)
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_gdma_copy {
union {
unsigned long src_offset; /*!< The offset of the source, based on the start address of its memory partition.
Use this parameter is only when @b src_use_phys = 0 and @b src_mmap_type are set properly. */
unsigned long src_addr; /*!< The physical address of the source. This parameter is used only when @b src_use_phys = 1. */
};
union {
unsigned long dst_offset; /*!< The offset of the destination based on the memory partition start address.
This parameter is used only when @b dst_use_phys = 0 and @b dst_mmap_type are set properly. */
unsigned long dst_addr; /*!< The physical address of the destination. This parameter is used only when @b dst_use_phys = 1. */
};
u16 src_pitch; /*!< Data pitch of the source */
u16 dst_pitch; /*!< Data pitch of the destination */
u16 src_use_phys : 1; /*!< A flag that determines whether @b src_addr or @b src_offset is used. */
u16 dst_use_phys : 1; /*!< A flag that determines whether @b dst_addr or @b dst_offset is used. */
u16 src_use_dma_buf_fd : 1; /*!< A flag that determines whether @b src_dma_buf_fd or @b src_mmap_type is used. */
u16 dst_use_dma_buf_fd : 1; /*!< A flag that determines whether @b dst_dma_buf_fd or @b dst_mmap_type is used. */
u16 src_skip_cache_sync : 1; /*!< The src buffer cache will not be synced if this flag is enabled. */
u16 dst_skip_cache_sync : 1; /*!< The dst buffer cache will not be synced if this flag is enabled. */
u16 reserved : 10;
u16 width; /*!< The width of the memory copy region */
u32 height; /*!< The height of the memory copy region */
union {
u32 src_mmap_type; /*!< The memory partition ID of the source */
int src_dma_buf_fd; /*!< The dma-buf:fd of the source */
};
union {
u32 dst_mmap_type; /*!< The memory partition ID of the destination */
int dst_dma_buf_fd; /*!< The dma-buf:fd of the destination */
};
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
#define MAX_POLL_EVENT (16)
#define POLL_EVENT_INDEX(bit) (1 << bit)
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_framedesc {
u32 id; /*!< Stream ID, -1 for read bits of all streams */
u32 time_ms; /*!< timeout in ms. -1 (0xFFFFFFFF) means non-blocking, 0 means blocking */
enum iav_stream_type stream_type; /*!< Stream type of the frame */
u32 pic_type : 3; /*!< Picture type of the frame */
u32 stream_end : 1; /*!< Flag for stream end */
u32 reserved0 : 4;
u32 jpeg_quality : 8; /*!< Quality value for MJPEG. Valid range [0~100]. */
u32 bitrate_kbps : 16; /*!< Real bitrate in kbps for H264 / H265 */
u32 reserved1;
u32 session_id; /*!< Session ID of the stream for each frame */
u32 size; /*!< Coded bits size for the frame, it is per slice or per tile */
u32 slice_id : 4; /*!< Slice ID */
u32 slice_num : 4; /*!< Total slice number */
u32 tile_id : 4; /*!< Tile ID */
u32 tile_num : 4; /*!< Total tile number */
u32 is_ltr_frame : 1; /*!< Is long term reference frame or not */
u32 force_frame_skip : 1; /*!< Is the frame skipped */
u32 reserved2 : 14;
u64 arm_pts; /*!< System PTS for the frame */
u64 dsp_pts; /*!< DSP PTS for the frame */
u64 enc_done_ts; /*!< The encode done time stamp for the frame */
struct iav_window reso; /*!< Resolution of the encoded frame */
unsigned long data_addr_offset; /*!< Address offset for frame coded bits */
unsigned long mv_data_offset; /*!< Byte offset for MV data, @sa iav_mv */
u32 cap_seq_no; /*!< Capture sequence number for frame */
u16 sliceheader_offset; /*!< Byte offset for the bit stream content data from each frame */
u16 encoded_frame_num; /*!< 16 bit frame number of the frame in encode order */
u64 frame_num; /*!< 64 bit frame number of the frame in display order */
unsigned long custom_sei_offset; /*!< Address offset for custom sei data */
};
struct iav_slicedesc {
u32 id; /*!< Stream ID, -1 for read bits of all streams */
u32 time_ms; /*!< timeout in ms; -1 (0xFFFFFFFF) means non-blocking, 0 means blocking */
enum iav_stream_type stream_type;/*!< Stream type of the frame */
u32 pic_type : 3; /*!< Picture type of the frame */
u32 stream_end : 1; /*!< Flag for stream end */
u32 force_frame_skip : 1; /*!< Is the frame skipped */
u32 reserved0 : 3;
u32 jpeg_quality : 8; /*!< Quality value for MJPEG. Valid range [0~100]. */
u32 bitrate_kbps : 16; /*!< Real bitrate in kbps for H264 / H265 */
u16 sliceheader_offset; /*!< Byte offset for the bit stream content data from each slice */
u16 reserved1;
u32 session_id; /*!< Session ID of the stream for the frame */
u64 arm_pts; /*!< System PTS for the frame */
u64 dsp_pts; /*!< DSP PTS for the frame */
u64 enc_done_ts; /*!< The encode done timestamp for the frame */
struct iav_window reso; /*!< Resolution of the encoded frame */
u32 slice_id : 4; /*!< Slice ID */
u32 slice_num : 4; /*!< Total slice number */
u32 tile_id : 4; /*!< Tile ID */
u32 tile_num : 4; /*!< Total tile number */
u32 encoded_frame_num : 16; /*!< 16 bit frame number of the frame in encode order */
u32 size[IAV_HEVC_TILE_NUM]; /*!< Coded bits size for the slice */
unsigned long data_addr_offset[IAV_HEVC_TILE_NUM]; /*!< Address offset for slice coded bits */
u64 frame_num; /*!< 64 bit frame number of the frame in display order */
};
/* mv descriptor reported by DSP */
struct iav_mv {
s32 x : 14; // Bit [13:0] is the x component in signed 14-bit format
s32 y : 13; // Bit [26:14] is the y component in signed 13-bit format
s32 reserved : 5;
};
struct iav_statisdesc {
u32 id; /*!< Stream ID, -1 for read bits of all streams */
u32 time_ms; /*!< timeout in ms; -1 (0xFFFFFFFF) means non-blocking, 0 means blocking */
u32 width; /*!< Width offset for frame */
u32 height; /*!< Height offset for frame */
u32 pitch; /*!< Pitch offset for frame */
u32 dsp_pts; /*!< DSP PTS for the frame */
u64 arm_pts; /*!< ARM PTS for the frame */
u32 frame_num; /*!< Frame number of the frame */
u32 session_id; /*!< Session ID */
u32 size; /*!< Unit size of the frame MV dump data when statis_type = IAV_ENC_STATIS_MV,
unit size of the frame for current bit-stream when statis_type = IAV_ENC_STATIS_BS_INFO. */
enum iav_statis_type statis_type; /*!< Statis type */
unsigned long data_addr_offset; /*!< Address offset for frame statistic data */
unsigned long data2_addr_offset; /*!< It is available when data2_addr_offset_valid = 1 */
u32 data2_addr_offset_valid : 1; /*!< Whether data2_addr_offset is valid or not. It is valid when dual core spatial is used. */
u32 reserved : 31;
};
struct iav_pre_framedesc {
u16 stream_id : 8; /*!< Stream ID, -1 for read bits of all streams */
u16 pic_type : 3; /*!< Frame type as I, P, B */
u16 is_ltr : 1; /*!< Long term reference P frame flag */
u16 get_latest : 1; /*!< 0: get the oldest from the frame queue; 1: always get the latest frame */
u16 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u16 reserved : 1;
u16 y_pitch; /*!< YUV data pitch */
u16 me1_pitch; /*!< ME1 data Pitch */
u16 me0_pitch; /*!< ME0 data Pitch */
u64 frame_no; /*!< Frame number */
unsigned long y_addr_offset; /*!< Y data offset */
unsigned long uv_addr_offset;/*!< UV data offset */
unsigned long me1_addr_offset; /*!< ME1 data offset */
unsigned long me0_addr_offset; /*!< ME0 data offset */
struct iav_window yuv_reso; /*!< YUV resolution */
struct iav_window me1_reso; /*!< ME1 resolution */
struct iav_window me0_reso; /*!< ME0 resolution */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u32 reserved1;
u64 mono_pts; /*!< Monotonic PTS of the frame data */
};
struct iav_pre_countdesc {
u32 non_block_flag : 1; /*!< Query without block flag */
u32 reserved : 31;
u8 stream_cap_count[IAV_STREAM_MAX_NUM_ALL]; /*!< Frame information count for every stream */
};
struct iav_rawbufdesc {
u32 vin_id : 8; /*!< VIN controller ID */
u32 non_block_flag : 1; /*!< Block read flag of the raw picture */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 format : 3; /*!< raw data format. */
u32 raw_compressed : 1; /*!< raw data compress flag. */
u32 packed : 1; /*!< raw data bits pack flag. */
u32 bits_per_pixel : 5; /*!< raw data pixel bits number. */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 mipi_vc_cap : 1; /*!< This flag is used for mipi vc data capture. */
u32 reserved1 : 2;
u32 delay_frames : 8; /*!< The delay frame num when querying the RAW data.
This is added for EIS feature, should be equal to eis_delay_cnt. */
u32 width; /*!< Width of the raw picture */
u32 width_in_byte; /*!< Width of the raw picture in byte */
u32 height; /*!< Height of the raw picture */
u32 pitch; /*!< Pitch size of the raw picture */
u64 mono_pts; /*!< Monotonic PTS of the raw picture */
unsigned long raw_addr_offset; /*!< Address offset for frame raw picture */
u32 dsp_pts; /*!< DSP PTS of the raw picture */
u32 ce_addr_offset; /*!< Contrast enhance image addr for RGB format data, chroma addr for YUV format data. */
u16 ce_pitch; /*!< Contrast enhance image pitch for RGB format data, chroma pitch for YUV format data. */
u16 ce_width; /*!< Contrast enhance image width for RGB format data, chroma width for YUV format data. */
u32 ce_width_in_byte; /*!< Contrast enhance image width in byte for RGB format data, chroma width in byte for YUV format data. */
u32 seq_num; /*!< Sequence number of the raw data. */
u64 feed_seq_num; /*!< The sequence number of current raw buffer for manual feed.
For IAV_IOC_RELEASE_RAW_BUF, when feed_seq_num is specified to -1(0xFFFFFFFFFFFFFFFF),
it will release all locked raw buffers. */
unsigned long raw_base_addr_offset; /* Address offset for DSP partition start address to RAW base */
};
struct iav_rawgrpdesc {
u32 vin_map; /*!< VIN controller ID map*/
u32 reserved;
struct iav_rawbufdesc raw[VIN_CONTROLLER_NUM];
};
struct iav_raw_slicebufdesc {
u32 vin_id : 8; /*!< VIN controller ID */
u32 slice_id : 8; /*!< The current ID of the RAW slice */
u32 slice_num : 8; /*!< The total slice number of RAW */
u32 non_block_flag : 1; /*!< Block read flag of the slice data */
u32 format : 3; /*!< RAW slice data format. */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 raw_compressed : 1; /*!< RAW slice data compress flag. */
u32 packed : 1; /*!< RAW slice data bits pack flag. */
u32 bits_per_pixel : 5; /*!< RAW slice data pixel bits number. */
u32 reserved0 : 27;
u32 raw_slice_width; /*!< Width of the RAW slice data */
u32 raw_slice_height; /*!< Height of the RAW slice data */
u32 raw_slice_pitch; /*!< Pitch size of the RAW slice data */
u32 width_in_byte; /*!< Width of the RAW slice data in byte */
u32 dsp_pts; /*!< DSP PTS of the RAW slice data */
u64 mono_pts; /*!< Monotonic PTS of the RAW slice data */
u32 seq_num; /*!< Sequence number of the RAW slice data. */
u16 raw_slice_ce_pitch; /*!< Contrast enhance image pitch of RAW slice data. */
u16 reserved1;
u32 ce_width_in_byte; /*!< Contrast enhance image width in byte. */
u16 raw_slice_ce_width; /*!< Contrast enhance image width of RAW slice data. */
u16 reserved2;
u64 feed_seq_num; /*!< The sequence number of current raw buffer for manual feed.
For IAV_IOC_RELEASE_RAW_BUF, when feed_seq_num is specified to -1(0xFFFFFFFFFFFFFFFF),
it will release all locked raw buffers. */
unsigned long raw_slice_addr_offset; /*!< Address offset of RAW slice data */
unsigned long raw_slice_ce_addr_offset; /*!< Contrast enhance image addr aoffset of RAW slice data. */
};
struct iav_rawseqdesc {
u32 vin_id : 8; /*!< VIN controller ID */
u32 non_block_flag : 1; /*!< Block read flag of the raw picture */
u32 reserved1 : 23;
u32 width; /*!< Width of the raw picture */
u32 height; /*!< Height of the raw picture */
u32 pitch; /*!< Pitch size of the raw picture */
unsigned long seq_pts[IAV_MAX_RAWSEQ_NUM]; /*!< DSP PTS of each frame from RAW sequence */
unsigned long seq_addr_offset[IAV_MAX_RAWSEQ_NUM]; /*!< Address offset of each frame from RAW sequence */
};
struct iav_y12_cap {
u32 width; /*!< Width of the Y12 data */
u32 height; /*!< Height of the Y12 data */
u32 pitch; /*!< Pitch size of the Y12 data */
u32 seq_num; /*!< Sequence number of the Y12 data */
u32 format; /*!< Format of the Y12 data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u64 mono_pts; /*!< Monotonic PTS of the Y12 data */
unsigned long y_addr_offset; /*!< Address offset for y12 data */
};
struct iav_c2y_raw_cap {
u32 width; /*!< Width of the c2y raw data in pixel */
u32 width_in_byte; /*!< Width of the c2y raw data in byte */
u32 height; /*!< Height of the c2y raw data */
u32 pitch; /*!< Pitch size of the c2y raw data */
u32 seq_num; /*!< Sequence number of the c2y raw data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u64 mono_pts; /*!< Monotonic PTS of the c2y raw data */
unsigned long raw_addr_offset; /*!< Address offset for c2y raw data */
};
struct iav_yuv_cap {
u32 width; /*!< Width of the YUV data */
u32 height; /*!< Height of the YUV data */
u32 pitch; /*!< Pitch size of the YUV data */
u32 seq_num; /*!< Sequence number of the YUV data */
u32 format; /*!< Format of the YUV data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u64 mono_pts; /*!< Monotonic PTS of the YUV data */
unsigned long y_addr_offset; /*!< Address offset for frame Y data */
unsigned long uv_addr_offset;/*!< Address offset for frame UV data */
};
struct iav_me_cap {
u32 width; /*!< Width of the frame ME data */
u32 height; /*!< Height of the frame ME data */
u32 pitch; /*!< Pitch size of the frame ME data */
u32 seq_num; /*!< Sequence number of the frame ME data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u32 reserved;
u64 mono_pts; /*!< Monotonic PTS of the frame ME data */
unsigned long data_addr_offset; /*!< Address offset for frame ME data */
};
struct iav_extraw_cap {
u32 width; /*!< Width of the custom c2y nn extra Raw data */
u32 height; /*!< Height of the custom c2y nn extra Raw data */
u32 pitch; /*!< Pitch size of the custom c2y nn extr Raw data */
u32 seq_num; /*!< Sequence number of the custom c2y nn extra Raw data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u32 reserved;
u64 mono_pts; /*!< Monotonic PTS of the custom c2y nn extra Raw data */
unsigned long raw_addr_offset; /*!< Address offset for custom c2y nn extra RAW data */
};
struct iav_mo_cap {
u32 width; /*!< Width of the motion data */
u32 height; /*!< Height of the motion data */
u32 pitch; /*!< Pitch size of the motion data */
u32 seq_num; /*!< Sequence number of the motion data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u32 part_id; /*!< Motion data based memory partiton item ID, @sa iav_mem_part_id */
u64 mono_pts; /*!< Monotonic PTS of the motion data */
unsigned long mo_addr_offset[IAV_MAX_MOTION_TYPE_NUM]; /*!< Address offset for motion data */
};
struct iav_deci_raw_cap {
u32 width; /*!< Width of the deci raw data in pixel */
u32 width_in_byte; /*!< Width of the deci raw data in byte */
u32 height; /*!< Height of the deci raw data */
u32 pitch; /*!< Pitch size of the deci raw data */
u32 seq_num; /*!< Sequence number of the deci raw data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u64 mono_pts; /*!< Monotonic PTS of the deci raw data */
unsigned long deci_addr_offset; /*!< Address offset for deci raw data */
};
struct iav_custom_aisp_bufdesc { /* Totally 256 bytes */
u32 chan_id : 8; /*!< Channel id */
u32 non_block_flag : 1; /*!< Block read flag of the custom aisp buffer info */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 reserved0 : 21;
u32 seq_num; /*!< seq_num of current custom aisp buffer */
u32 dag_addr; /*!< the dag address of network used to produce images */
u32 reserved1[17];
struct iav_extraw_cap c2y_raw; /*!< current custom aisp c2y_raw buffer */
struct iav_yuv_cap c2y_yuv; /*!< current custom aisp c2y_yuv buffer */
struct iav_yuv_cap nn_yuv; /*!< current custom aisp nn_yuv buffer */
struct iav_me_cap nn_me1; /*!< current custom aisp nn_me1 buffer */
};
struct iav_extra_raw_cap {
u8 vinc_id; /*!< Vin controller id*/
u8 reserved[3];
u32 pitch; /*!< Pitch of extra raw data */
u16 height; /*!< Height of extra raw data */
u8 top_lines; /*!< Top lines of extra raw data */
u8 bottom_lines; /*!< Bottom lines of extra raw data */
u32 dsp_pts; /*!< Intermediate PTS from DSP */
u64 mono_pts; /*!< Monotonic PTS of the frame ME data */
unsigned long data_addr_offset; /*!< Data addr offset of extra raw data */
};
struct iav_y12desc {
u32 chan_id : 8; /*!< Chan ID */
u32 non_block_flag : 1; /*!< Block flag */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 y12_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe Y12 data. */
u32 packed : 1; /*!< Data store fomat. */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 bits_per_pixel : 8; /*!< Y12 data pixel bits number. */
u32 reserved : 11;
struct iav_y12_cap y12; /*!< Y12 descriptor item */
int y12_dma_buf_fd; /*!< Fd of y12 data, only valid when y12_use_dma_buf_fd is set */
};
struct iav_c2y_raw_desc {
u32 chan_id : 8; /*!< Chan ID */
u32 non_block_flag : 1; /*!< Block flag */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 c2y_raw_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe c2y raw data. */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 bits_per_pixel : 8; /*!< c2y raw data pixel bits number. */
u32 reserved : 12;
struct iav_c2y_raw_cap c2y_raw; /*!< c2y raw descriptor item */
int c2y_raw_dma_buf_fd; /*!< Fd of c2y raw data, only valid when c2y_raw_use_dma_buf_fd is set */
};
struct iav_deci_raw_desc {
u32 chan_id : 8; /*!< Chan ID */
u32 non_block_flag : 1; /*!< Block flag */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 deci_raw_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe deci raw data. */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 bits_per_pixel : 8; /*!< Deci raw data pixel bits number. */
u32 reserved : 12;
struct iav_deci_raw_cap deci_raw; /*!< Deci raw descriptor item */
int deci_raw_dma_buf_fd; /*!< Fd of deci raw data, only valid when deci_raw_use_dma_buf_fd is set */
};
struct iav_canvasdesc {
u32 canvas_id : 8; /*!< Canvas ID */
u32 non_block_flag : 1; /*!< Block flag */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 yuv_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe YUV data. */
u32 me_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe ME data. */
u32 query_extra_raw : 1; /*!< This is to specify if querying extra raw info */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 discard_cached_items : 1; /*!< When set, discard cached items and wait for the next coming one.
Only valid when non_block_flag is 0. */
u32 mo_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe the motion stream data. */
u32 lifetime : 16; /*!< The expired time (ms) for this canvas starting from idsp_proc_done_pts.
Only valid when manual_feed is not set.*/
struct iav_yuv_cap yuv; /*!< YUV descriptor item */
struct iav_me_cap me1; /*!< ME1 descriptor item */
struct iav_me_cap me0; /*!< ME0 descriptor item */
u64 feed_seq_num; /*!< The sequence number of current canvas buffer for manual feed.
For IAV_IOC_RELEASE_CANVAS_BUF, when feed_seq_num is specified to -1(0xFFFFFFFFFFFFFFFF),
it will release all locked canvas buffers. */
int yuv_dma_buf_fd; /*!< The dma-buf:fd of YUV data, only valid when yuv_use_dma_buf_fd is set */
int me_dma_buf_fd; /*!< The dma-buf:fd of ME data (ME0 and ME1 share the same dma-buf:fd),
only valid when me_use_dma_buf_fd is set */
struct iav_extra_raw_cap extra_raw; /*!< Extra raw data descriptor item */
u64 idsp_proc_done_pts; /*!< The IDSP processing done timestamp for the canvas */
u64 sync_task_id; /*!< The task ID of IDSP_ENC sync task taking effect in this frame. */
struct iav_mo_cap mo; /*!< The motion stream descriptor item. Note: mo_addr_offset[0] and mo_addr_offset[1]
represent the same motion address. */
int mo_dma_buf_fd; /*!< The dma-buf:fd of the motion stream data, only valid when mo_use_dma_buf_fd
is set */
u32 is_broken : 1; /* Whether the frame is broken or not. If it is broken, the frame would be the dummy frame
for vsync loss or preview with broken sensor cases. */
u32 reserved1 : 31;
u32 reserved[15]; /*!< Aligned to 320 Bytes */
};
struct iav_canvasgrpdesc {
u32 canvas_id_map; /*!< As input param, specify the canvas id map for querying. As output param, return the
actually queried canvas id map. */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 non_block_flag : 1; /*!< Block flag */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 yuv_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe YUV data. */
u32 me_use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe ME data. */
u32 discard_cached_items : 1; /*!< When set, discard cached items and wait for the next coming one.
Only valid when non_block_flag is 0. */
u32 reserved : 26;
struct iav_yuv_cap yuv[IAV_MAX_CANVAS_BUF_NUM_IMPL]; /*!< YUV descriptor item */
struct iav_me_cap me1[IAV_MAX_CANVAS_BUF_NUM_IMPL]; /*!< ME1 descriptor item */
struct iav_me_cap me0[IAV_MAX_CANVAS_BUF_NUM_IMPL]; /*!< ME0 descriptor item */
int yuv_dma_buf_fd[IAV_MAX_CANVAS_BUF_NUM_IMPL]; /*!< The dma-buf:fd of YUV data, only valid when
yuv_use_dma_buf_fd is set */
int me_dma_buf_fd[IAV_MAX_CANVAS_BUF_NUM_IMPL]; /*!< The dma-buf:fd of ME data (ME0 and ME1 share the same
dma-buf:fd), only valid when me_use_dma_buf_fd is set */
u64 idsp_proc_done_pts; /*!< The IDSP processing done timestamp for the canvas group */
u16 lifetime[IAV_MAX_CANVAS_BUF_NUM_IMPL]; /*!< The expired time (ms) for this canvas starting from idsp_proc_done_pts.
Only valid when manual_feed is not set.*/
};
struct iav_blenddesc {
u32 canvas_id : 8; /*!< Canvas ID for the blend overlap area query */
u32 non_block_flag : 1; /*!< Block read flag of the blend description */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 reserved : 22;
struct iav_yuv_cap yuv[IAV_BLEND_OVERLAP_AREA_MAX][IAV_BLEND_NUM]; /*!< YUV buffer information of overlapped areas */
};
struct iav_pyramiddesc {
u32 chan_id : 8; /*!< Channel ID */
u32 non_block_flag : 1; /*!< Block read flag of the pyramid description */
u32 layers_map : 7; /*!< Layer bit map. Each bit stands for one layer. 1 means enable this layer, 0 means disable
this layer. */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe pyramid frame.
NOTE: it is only valid for querying pyramid data in manual-feed mode. */
u32 query_extra_raw : 1;/*!< This is to specify if querying extra raw info */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 is_broken : 1; /* Whether the frame is broken or not. If it is broken, the frame would be the dummy frame
for vsync loss or preview with broken sensor cases. */
u32 reserved : 11;
struct iav_yuv_cap layers[IAV_MAX_PYRAMID_LAYERS]; /*!< YUV buffer information of enabled pyramid layers */
u64 seq_num; /*!< The sequence number of current pyramid description. For IAV_IOC_RELEASE_PYRAMID_BUF,
when seq_num is set to -1(0xFFFFFFFFFFFFFFFF), it will release all locked pyramid buffers. */
int dma_buf_fd; /*!< dma-buf:fd of current pyramid frame. Only valid when @b use_dma_buf_fd = 1 */
struct iav_extra_raw_cap extra_raw; /*!< Extra raw data descriptor item */
u64 idsp_proc_done_pts; /*!< The IDSP processing done timestamp for the pyramid */
};
struct iav_motiondesc {
u32 chan_id : 8; /*!< Channel ID */
u32 non_block_flag : 1; /*!< Block read flag of the motion description */
u32 is_dsp_hw_pts : 1; /*!< When set, dsp_pts is hw_pts from dsp, otherwise sw_pts. */
u32 use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe mo frame.
NOTE: it is only valid for querying motion data in manual-feed mode. */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 is_hdr_md: 1; /*!< When set, the output motion will be HDR MD motion stream. */
u32 reserved : 19;
struct iav_mo_cap mo_cap; /*!< Motion data buffer information of enabled motion data output */
u64 seq_num; /*!< The sequence number of current motion data description. For IAV_IOC_RELEASE_MO_BUF,
when seq_num is set to -1(0xFFFFFFFFFFFFFFFF), it will release all locked motion data buffers. */
int dma_buf_fd; /*!< dma-buf:fd of current motion data. Only valid when @b use_dma_buf_fd = 1 */
u64 idsp_proc_done_pts; /*!< The IDSP processing done timestamp for the motion data */
};
struct iav_match_table {
unsigned long addr_offset; /*!< Address offset based on blend alpha partition */
u32 offset_x; /*!< Address offset in the overlap area */
u32 grid_space_h; /*!< Grid spacing in horizontal direction */
u32 grid_space_v; /*!< Grid spacing in vertical direction */
u32 grid_rows; /*!< Grid rows */
u32 grid_cols; /*!< Grid cols */
};
struct iav_blend_area_pair {
u8 chan_id[IAV_BLEND_NUM]; /*!< Channel IDs to which blend areas belong */
u16 width; /*!< YUV buffer width of blend area */
u16 height; /*!< YUV buffer height of blend area */
u16 pitch; /*!< YUV buffer pitch of blend area */
u32 hw_pts; /*!< DSP hardware PTS of YUV buffer */
u32 format : 2; /*!< YUV buffer format */
u32 match_table_valid : 1; /*!< This is a flag showing whether match_table is provided. */
u32 reserved0 : 29;
u32 seq_num; /*!< sequence number of YUV buffer */
u32 reserved1;
u64 mono_pts; /*!< Monotonic PTS of YUV buffer */
unsigned long y_addr_offset[IAV_BLEND_NUM]; /*!< Y buffer offset */
unsigned long uv_addr_offset[IAV_BLEND_NUM]; /*!< UV buffer offset */
struct iav_match_table match_table; /*!< Overlap match table configuration.
When it is provided, match_table_valid will be set as 1. */
};
struct iav_blend_areas {
u8 img_stats_group_idx : 2; /*!< IN: the group index where the channels' stats is grouped.
This param is for future purpose when there are two or more groups of channels
doing cross-channel stitching separately. At current, just set it as 0. */
u8 non_block_flag : 1; /*!< IN: Block read flag of the blend description */
u8 is_warped : 1; /*!< OUT: this is a flag showing whether the stitching dewarp is applied or not. */
u8 active_area_pair_num : 4; /*!< OUT: Active overlap area pair number. */
u8 canvas_id; /*!< OUT: Canvas ID for the blending target canvas(main buffer canvas) */
u8 reserved1[2];
u32 reserved2[5];
struct iav_blend_area_pair area_pair[IAV_BLEND_OVERLAP_AREA_MAX]; /*!< OUT: Blend area YUV information */
};
struct iav_blend_match_table {
u8 canvas_id; /*!< IN: Canvas ID for the blend overlap area */
u8 reserved;
u16 area_id_map; /*!< IN/OUT: Active overlap area ID. */
struct iav_match_table match_table[IAV_BLEND_OVERLAP_AREA_MAX]; /*!< IN/OUT: Overlap match table configuration. */
};
struct iav_overlap_area {
u16 width; /*!< Width of blend overlap area. */
u16 height; /*!< Height of blend overlap area. */
u16 pitch; /*!< Pitch of blend overlap area. It must be alighed to 64 bytes. */
u16 update_alpha_enable : 1; /*!< This is a flag to enable / disable updating alpha table. */
u16 reserved0 : 15;
u8 chan_id[IAV_BLEND_NUM]; /*!< Channel ID of overlapped areas */
u8 padding[IAV_BLEND_NUM]; /*!< Padding of overlapped areas. Read Only */
unsigned long alpha_addr_offset[IAV_BLEND_NUM]; /*!< Offset of Alpha table memory */
};
struct iav_blend_overlap {
u8 canvas_id; /*!< Quried canvas id. */
u8 active_overlap_num; /*!< Active blend overlap number. @sa IAV_BLEND_OVERLAP_AREA_MAX */
u8 reserved[2];
u32 mem_part_offset; /*!< Memory offset in IAV_PART_BLEND_ALPHA */
u32 total_mem_size; /*!< Memory size in IAV_PART_BLEND_ALPHA */
struct iav_overlap_area mc_overlap[IAV_BLEND_OVERLAP_AREA_MAX]; /*!< Overlap area configuration */
};
struct iav_blend_dptz_info {
u32 enable : 1; /*!< Blend DPTZ enable flag */
u32 reserved : 31;
struct iav_rect input; /*!< Blend DPTZ input window */
struct iav_rect output; /*!< Blend DPTZ output window */
};
struct iav_blend_dptz {
struct iav_blend_dptz_info dptz[IAV_SRCBUF_NUM]; /*!< Blend DPTZ configuration */
};
struct iav_framedesc_event {
u32 stream_id; /*!< Stream ID, -1 for read bits of all streams */
};
struct iav_statisdesc_event {
u32 stream_id; /*!< Stream ID, -1 for read bits of all streams */
enum iav_statis_type statis_type; /*!< Statis type */
};
struct iav_rawbufdesc_event {
u8 vin_id; /*!< VIN controller ID */
u8 reserved[3];
};
struct iav_rawseqdesc_event {
u8 vin_id; /*!< VIN controller ID */
u8 reserved[3];
};
struct iav_canvasdesc_event {
u8 canvas_id; /*!< Canvas ID */
u8 reserved[3];
};
struct iav_y12desc_event {
u8 chan_id; /*!< Channel ID */
u8 reserved[3];
};
struct iav_pyramiddesc_event {
u8 chan_id; /*!< Channel ID */
u8 reserved[3];
};
struct iav_slicedesc_event {
u32 stream_id; /*!< Stream ID, -1 for read bits of all streams */
};
struct iav_c2yrawdesc_event {
u8 chan_id; /*!< Channel ID */
u8 reserved[3];
};
struct iav_deci_rawdesc_event {
u8 chan_id; /*!< Channel ID */
u8 reserved[3];
};
struct iav_querydesc_event {
enum iav_desc_id qid; /*!< query desc id */
union {
struct iav_framedesc_event frame; /*!< query frame event */
struct iav_slicedesc_event slice; /*!< query slice event */
struct iav_statisdesc_event statis; /*!< query encoding statis event */
struct iav_rawbufdesc_event rawbuf; /*!< query single raw image event */
struct iav_rawseqdesc_event rawseq; /*!< query raw image sequence event */
struct iav_canvasdesc_event canvas; /*!< query single canvas event */
struct iav_pyramiddesc_event pyramid; /*!< query pyramid event */
struct iav_y12desc_event y12; /*!< query y12 event */
struct iav_c2yrawdesc_event c2y_raw; /*!< query c2y raw event */
struct iav_deci_rawdesc_event deci_raw; /*!< query deci raw event */
} arg;
};
struct iav_poll_event_config {
u8 valid_num; /*!< query event num */
u8 reserved[3];
struct iav_querydesc_event desc_event[MAX_POLL_EVENT]; /*!< detailed event */
};
struct iav_querydesc {
enum iav_desc_id qid; /*!< query desc id */
union {
struct iav_framedesc frame; /*!< query frame */
struct iav_statisdesc statis; /*!< query encoding statis */
struct iav_rawbufdesc raw; /*!< query single raw image */
struct iav_rawgrpdesc rawgrp; /*!< query raw images of grouped VIN controllers */
struct iav_rawseqdesc rawseq; /*!< query raw image sequence */
struct iav_canvasdesc canvas; /*!< query single canvas */
struct iav_y12desc y12; /*!< query single y12 image */
struct iav_canvasgrpdesc canvasgrp; /*!< query group of canvas */
struct iav_slicedesc slice; /*!< query frame slice */
struct iav_pyramiddesc pyramid; /*!< query pyramid */
struct iav_blenddesc blend; /*!< query blend */
struct iav_pre_framedesc pre_frame; /*!< query pre frame info */
struct iav_pre_countdesc pre_count; /*!< query pre frame count */
struct iav_custom_aisp_bufdesc custom_aisp; /*!< query custom aisp buffer info */
struct iav_raw_slicebufdesc raw_slice; /*!< query raw slice info */
struct iav_motiondesc motion; /*!< query motion data */
struct iav_blend_areas blend_areas; /*!< query blend areas */
struct iav_c2y_raw_desc c2y_raw; /*!< query c2y raw image */
struct iav_deci_raw_desc deci_raw; /*!< query deci raw image */
} arg;
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
#define AVC_HIST_X (16)
#define HEVC_MV_HIST_X (2)
#define HEVC_MV_HIST_Y (2)
#define HEVC_MV_HIST_K (128)
#define HEVC_QP_HIST_X (64)
#define HEVC_INTER_CNT_U8_X (5)
#define HEVC_INTER_CNT_U16_X (3)
#define HEVC_INTER_CNT_U32_X (3)
enum iav_stream_op {
IAV_STREAM_OP_STOP = 0, /*!< 0 */
IAV_STREAM_OP_START = 1, /*!< 1 */
};
enum iav_chroma_format {
H264_CHROMA_YUV420 = 0, /*!< 0 */
H264_CHROMA_MONO = 1, /*!< 1 */
JPEG_CHROMA_MONO = 0, /*!< 0 */
JPEG_CHROMA_YUV420 = 1, /*!< 1 */
JPEG_CHROMA_YUV422 = 2, /*!< 2 */
};
enum GOP_IDR_INTV {
MIN_IDR_INTV = 1, /*!< 1 */
MAX_IDR_INTV = 128, /*!< 128 */
};
typedef enum {
QP_FRAME_I = 0, /*!< 0 */
QP_FRAME_P = 1, /*!< 1 */
QP_FRAME_B = 2, /*!< 2 */
QP_FRAME_TYPE_NUM = 3, /*!< 3 */
} QP_FRAME_TYPES;
typedef enum {
QPROI_TYPE_CATEGORY = 0, /*!< 0 */
QPROI_TYPE_QP_OFFSET = 1, /*!< 1 */
} QPROI_TYPE;
typedef enum {
MD_CAT_LUT_TYPE_DEFAULT = 0, /*!< 0, For this CTB, it's coded as default option from DSP internal RC. */
MD_CAT_LUT_TYPE_FORCED_ZMV = 1, /*!< 1, For this CTB, it's forced to code with Zero Motion Vector (ZMV). */
MD_CAT_LUT_TYPE_FORCED_INTRA = 2, /*!< 2, For this CTB, it's forced to code as intra. */
MD_CAT_LUT_TYPE_UNCOVERED_AREA = 3, /*!< 3, For this CTB, it's detected to be uncovered and is not expected to
get good prediction from any of its references. It will be coded as intra.
In conjunction, ARM should config a negative QP adjust value for these
CTBs so that they are coded as high quality. */
MD_CAT_LUT_TYPE_BIAS_SKIP = 4, /*!< 4, For this CTB, it's bias heavily towards skipped. */
/* more to come */
MD_CAT_LUT_NUM = 5, /*!< 5 */
MD_CAT_LUT_FIRST = MD_CAT_LUT_TYPE_DEFAULT, /*!< MD_CAT_LUT_TYPE_DEFAULT */
MD_CAT_LUT_LAST = MD_CAT_LUT_NUM, /*!< MD_CAT_LUT_NUM */
MD_CAT_MAX_NUM = 8, /*!< 8 */
} MD_CAT_LUT_TYPE;
#define IAV_MAX_CU_BIAS_LEVEL 6
typedef enum {
H26X_SCALELIST_OFF = 0, /*!< 0 */
H26X_SCALELIST_DEFAULT = 1, /*!< 1 */
H26X_SCALELIST_CUSTOM = 2, /*!< 2 */
H26X_SCALELIST_TYPE_NUM = 3, /*!< 3 */
} H26X_SCALELIST_TYPE;
typedef enum {
H26X_SCALELIST_STRENGTH_OFF = 0, /*!< Off the system strength config, user can use customized scalelist configuration. */
H26X_SCALELIST_STRENGTH_LOW = 1, /*!< Low strength */
H26X_SCALELIST_STRENGTH_MEDIUM = 2, /*!< Medium strength */
H26X_SCALELIST_STRENGTH_HIGH = 3, /*!< High strength */
H26X_SCALELIST_STRENGTH_NUM = 4,
H26X_SCALELIST_STRENGTH_FIRST = H26X_SCALELIST_STRENGTH_OFF,
H26X_SCALELIST_STRENGTH_LAST = H26X_SCALELIST_STRENGTH_NUM,
} IAV_H26X_SCALELIST_STRENGTH;
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_pic_stats_avc {
/* h264_xfHisto_t */
u16 xfMbCatHisto[AVC_HIST_X]; /*!< Macro blocks number with corresponding QP value */
u32 reserved1[32];
/* Nom QP Table */
u8 qp[AVC_HIST_X]; /*!< QP values used in one encoded frame*/
u32 reserved[1044];
};
struct iav_pic_stats_hevc {
u32 rsvd0[542];
u32 qp_histogram[64]; /*!< QP value at CU8 granularity */
u32 rsvd1[482];
};
struct iav_stream_fps {
u32 fps_multi; /*!< Multiple value for fps configuration */
u32 fps_div; /*!< Divisor value for fps configuration */
u32 abs_fps : 8; /*!< Absolute frame rate value. Only valid when @b abs_fps_enable is set. */
u32 abs_fps_enable : 1; /*!< Flag to enable / disable abs FPS */
u32 is_update_frame_rate_to_next_GOP: 1; /*!< Flag to update frame rate to next GOP. */
u32 reserved : 22;
u32 abs_fps_hp; /*!< High precision framerate. abs_fps_hr = 1000 * abs_fps. For setting, only valid when "enable_hp_fps" is 1.
For getting, value is always valid.*/
};
struct iav_stream_flip {
u32 h : 1; /*!< Horizontal flip flag */
u32 v : 1; /*!< Vertical flip flag */
u32 reserved : 30;
};
struct iav_stream_format {
enum iav_stream_type type;/*!< @sa iav_stream_type */
struct iav_rect enc_win;/*!< Encode window from source buffer */
u32 duration : 16; /*!< Encode duration (in frames) for the stream */
u32 enc_src_id : 8; /*!< Encode source canvas id, 0~19: Canvas 0~19, 24: EFM */
u32 hflip : 1; /*!< Stream horizontal flip flag. 0: No horizontal flip; 1: Horizontal flip */
u32 vflip : 1; /*!< Stream vertical flip flag. 0: No vertical flip; 1: Vertical flip */
u32 rotate_cw : 1; /*!< Stream clockwise 90 rotation flag.
0: No clockwise rotation of 90; 1: Clockwise rotation of 90. */
u32 use_enc_src_map : 1; /*!< Flag to use enc_src_id or enc_src_map. 0: use enc_src_id; 1: use enc_src_map */
u32 fake_avg_pts : 1; /*!< Flag to enable the faked average PTS or not, default is disabled (0).
This feature is ONLY used when IDSP fps is upsampled from VIN frame rate.*/
u32 reserved0 : 3;
u32 efm_customize_fps; /*!< Specify the arbitrary frame rate for EFM stream */
u32 session_id; /*!< Specify the session id for the stream.
0: generate session id automatically; Non-zero: should be unique for each stream. */
u32 enc_src_map; /*!< Encode source canvas bit map. Stream can be encoded from multi-canvas with same resolution and offset. */
};
struct iav_fps_suggest {
u32 fps_keep_map; /*!< Bit map for stream fps keep or not: 1: Keep; 0: Not keep */
u32 stream_exclude_map; /*!< Bit map for stream exclusion: 1: Exclude; 0: Not exclude */
u32 stream_fps_suggest[IAV_STREAM_MAX_NUM_ALL]; /*!< Stream FPS suggest result in 16.16 Format */
u32 vin_target_fps[VIN_INSTANCES]; /*!< VIN target fps in 16.16 Format */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
#define IAV_MJPEG_MAX_SLICE_NUM (16)
#define IAV_MJPEG_MAX_SLICE_MB_NUM (0x10000)
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_h26x_gop {
u32 id; /*!< Related stream id. */
u32 N; /*!< GOP length. */
u32 idr_interval; /*!< GOP number between two idr.*/
u32 is_update_N_to_next_GOP : 1; /*!< Flag to GOP length update mode. 0: Update immediately.
1: Update at next gop (obsolete, N is always updated in current GOP but not next GOP). */
u32 reserved0 : 31;
};
struct iav_bitrate {
u32 id; /*!< Stream ID */
u32 average_bitrate; /*!< The target average bitrate */
u32 vbr_setting : 8; /*!< 1: IAV_BRC_CBR (obsolete); 2: IAV_BRC_PCBR (obsolete); 3: IAV_BRC_VBR (obsolete);
4: IAV_BRC_SCBR; 5: IAV_BRC_SVBR (obsolete). This field must always be set to IAV_BRC_SCBR (Smart Constant Bitrate Control). */
u32 qp_min_on_I : 8; /*!< This field specifies the minimum QP allowed for I picture. The valid range is 0 to 51 (inclusive).
The default value is 14. */
u32 qp_max_on_I : 8; /*!< This field specifies the maximum QP allowed for I picture. The valid range is 0 to 51 (inclusive).
The default value is 51. */
u32 qp_min_on_P : 8; /*!< This field specifies the minimum QP allowed for P picture. The valid range is 0 to 51 (inclusive).
The default value is 17. */
u32 qp_max_on_P : 8; /*!< This field specifies the maximum QP allowed for P picture. The valid range is 0 to 51 (inclusive).
The default value is 51. */
u32 qp_min_on_B : 8; /*!< This field specifies the minimum QP allowed for B picture. Not supported yet. */
u32 qp_max_on_B : 8; /*!< This field specifies the maximum QP allowed for B picture. Not supported yet. */
u32 i_qp_reduce : 8; /*!< This field specifies how much better to make I QP relative to P QP. To increase the ratio of I QP/ P QP,
use a small value. To reduce the ratio of I QP/ P QP, use a large value. The valid range is 1 to 10 (inclusive).
The default value is 6. */
u32 p_qp_reduce : 8; /*!< This field specifies how much better to make P QP relative to B QP. To increase the ratio of P QP/ B QP,
use a small value. To reduce the ratio of P QP/ B QP, use a large value. The valid range is 1 to 5 (inclusive).
The default value is 3. */
u32 adapt_qp : 8; /*!< This field specifies the strength of adaptive quantization. The valid range is 0 to 4 (inclusive).
The default value is 2. */
u32 skip_flag : 8; /*!< When smart RC is used (bitrate_control = 4), this field specifies the criteria for RC to skip frames.(Bitwise OR)
Bit 0: RC will skip the frame based on the size of the compressed picture.
Bit 1: RC will skip the frame based on CPB size.
Bit 2: RC will skip the frame when the target bit rate is to be exceeded and the maximum QP is reached.
The default value is 0 (no frame skipping). */
u32 q_qp_reduce : 8; /*!< Relative to P frame */
u32 qp_max_on_Q : 8; /*!< Maximum QP allowed for Q frame */
u32 qp_min_on_Q : 8; /*!< Minimum QP allowed for Q frame */
u32 log_q_num_minus_1 : 3; /*!< 128 */
u32 skip_flag_mode : 1; /*!< skip mode flag. 0: handle skip frame through drop frame. 1: through repeat frame.*/
u32 max_skip_num : 8; /*!< the max number of frames that can be skipped in continuous. It is only valid when skip_flag is set. */
u32 reserved0 : 4;
u32 max_i_size_KB; /*!< Maximum I frame size */
u32 qp_min_on_C : 8; /*!< This field specifies the minimum QP allowed for C picture. The valid range is 0 to 51 (inclusive).
The default value is 21. */
u32 qp_max_on_C : 8; /*!< This field specifies the maximum QP allowed for C picture. The valid range is 0 to 51 (inclusive).
The default value is 51. */
u32 qp_min_on_D : 8; /*!< This field specifies the minimum QP allowed for D picture. The valid range is 0 to 51 (inclusive).
The default value is 21. */
u32 qp_max_on_D : 8; /*!< This field specifies the maximum QP allowed for D picture. The valid range is 0 to 51 (inclusive).
The default value is 51. */
u32 b_qp_reduce : 8; /*!< This field specifies how much better to make b QP relative to B QP. To increase the ratio of b QP/ P-QP,
use a small value. To reduce the ratio of B QP/ P QP, use a large value. The valid range is 0 to 5 (inclusive).
The default value is 0. */
u32 c_qp_reduce : 8; /*!< This field specifies how much better to make c QP relative to B QP. To increase the ratio of b QP/ P-QP,
use a small value. To reduce the ratio of C QP/ P QP, use a large value. The valid range is 0 to 5 (inclusive).
The default value is 0. */
u32 cbr_stable_br_adjust : 4; /*!< This field specifies how much stable encoder tries to keep the real bitrate around average_bitrate.
The valid range is 0 to 10 (inclusive). 0: disable; 1: the most stable; 10: the least stable. */
u32 reserved1 : 12;
u32 vbr_min_bitrate; /*!< obsolete */
u32 vbr_max_bitrate; /*!< obsolete */
};
struct iav_h26x_weighted_pred {
u16 wp_enable; /*!< Enable Weighted Prediction */
u16 luma_log2_weight_denom; /*!< Specify luma-log2-wegiht-denom */
s16 luma_weight[2]; /*!< Set luma-weight[0]/luma-weight[1] */
s16 luma_offset[2]; /*!< Set luma-offset[0]/luma-offset[1] */
};
struct iav_rc_strategy {
u32 abs_br_flag : 1; /*!< Flag for abs_br */
u32 reserved : 31;
};
struct iav_h264_qproi_data {
u8 category; /*!< Macroblock level control for user_class */
s8 qp_adjust; /*!< Macroblock level control for qp_offset. The qp_offset is added onto
the existing QP already calculated by RC and User class bin. The final
QP from RC + qp_offset is then used for this MB. */
u8 zmv_threshold_val; /*!< Macroblock level control of threshold for zero MV. If MB's sum of Mvs
is less than this value, skip mode is encouraged. Value 8 can be used
for low bit rate at good lighting. Value 24 can be used for low bit
rate at low lighting (high noise). */
u8 force_zmv_ref0 : 1; /*!< Macroblock level control to force zmv on reference candidate 0. When
this flag is on, force zero MV will be adopted for the target MB, if
reference 0 is used. */
u8 force_zmv_ref1 : 1; /*!< Macroblock level control to force zmv on reference candidate 1. When
this flag is on, force zero MV will be adopted for the target MB, if
reference 1 is used. */
u8 reserved : 6;
};
struct iav_h265_qproi_data {
union {
struct {
u32 cu16_0 : 3; /*!< Select md_category for 16x16 CU[0]. 0: default; 1: used as force zmv flag. */
u32 cu16_1 : 3; /*!< Select md_category for 16x16 CU[1]. 0: default; 1: used as force zmv flag. */
u32 cu16_2 : 3; /*!< Select md_category for 16x16 CU[2]. 0: default; 1: used as force zmv flag. */
u32 cu16_3 : 3; /*!< Select md_category for 16x16 CU[3]. 0: default; 1: used as force zmv flag. */
u32 cu32 : 3; /*!< Select md_category for 32x32 CU. 0: default; 1: used as force zmv flag. */
u32 reserved_0 : 17;
};
u32 dword1;
} category;
union {
struct {
s32 reserved_1 : 8;
s32 cu32 : 7; /*!< qp_adjust value for 32x32 CU. Valid range of -51 to 51 inclusive. */
s32 reserved_2 : 17;
};
u32 dword2;
} qp_adjust_32;
union {
struct {
s32 cu16_0 : 7; /*!< qp_adjust value for 16x16 CU[0]. Valid range of -51 to 51 inclusive. */
s32 reserved_3 : 1;
s32 cu16_1 : 7; /*!< qp_adjust value for 16x16 CU[1]. Valid range of -51 to 51 inclusive. */
s32 reserved_4 : 1;
s32 cu16_2 : 7; /*!< qp_adjust value for 16x16 CU[2]. Valid range of -51 to 51 inclusive. */
s32 reserved_5 : 1;
s32 cu16_3 : 7; /*!< qp_adjust value for 16x16 CU[3]. Valid range of -51 to 51 inclusive. */
s32 reserved_6 : 1;
};
u32 dword3;
} qp_adjust_16;
u32 reserved_7;
};
struct iav_qpmatrix {
u32 id; /*!< Stream ID */
u32 enable : 1; /*!< whether qp matrix is enabled */
u32 qpm_no_update : 1; /*!< 1: No need from app to set the QP matrix data to IAV/DSP, just configure some other parameters.
0: App needs to set the QP matrix data (already configured at app side) to IAV/DSP. */
u32 qpm_no_check : 1; /*!< 1: No need for IAV to check the QP matrix data to IAV/DSP, app already guarantees the validness
for the qp matrix data.
0: IAV needs to check the QP matrix data (already configured at app side) to IAV/DSP. */
u32 init_qpm : 1; /*!< Init QP matrix flag to set OP */
u32 qpm_raw : 1; /*!< QP matrix raw mapped flag for get/set op */
u32 reserved0 : 27;
u32 data_size; /*!< The size for the QP ROI matrix */
u32 reserved1;
unsigned long data_offset; /*!< The address offset for the QP ROI. The structure @sa iav_h264_qproi_data
or @sa iav_h265_qproi_data shows the data format. */
};
struct iav_h26x_enc_param {
u32 id; /*!< Stream ID */
u16 user1_intra_bias; /*!< The intra bias for user class 1, range from 0 to 65535 */
u16 user1_direct_bias; /*!< The direct bias for user class 1, range from 0 to 65535 */
u16 user2_intra_bias; /*!< The intra bias for user class 2, range from 0 to 65535 */
u16 user2_direct_bias; /*!< The direct bias for user class 2, range from 0 to 65535 */
u8 intra_bias_override_usr1 : 1; /*!< User1 intra bias mode, 0: add, 1: override */
u8 direct_bias_override_usr1 : 1; /*!< User1 direct bias mode, 0: add, 1: override */
u8 intra_bias_override_usr2 : 1; /*!< User2 intra bias mode, 0: add, 1: override */
u8 direct_bias_override_usr2 : 1; /*!< User2 direct bias mode, 0: add, 1: override */
u8 reserved0 : 4;
u8 reserved1[3];
};
struct iav_h26x_slice {
u32 slice_num : 8; /*!< Specify slice row number, from 0~255. */
u32 slices_per_info : 8;/*!< Specify slices per bits information. */
u32 reserved : 16;
};
struct iav_h26x_pskip {
u32 repeat_enable : 1; /*!< Enable repeat P-skip frame pattern */
u32 repeat_mode : 1; /*!< Specify P-skip repeat mode.
0: consider the skip num as the interval between every
two normal P frames.
1: consider the skip num as the interval between every
two Pskip frames.*/
u32 reserved0 : 14;
u32 repeat_num : 8; /*!< Specify the skipped frame number to repeat */
u32 reserved1 : 8;
};
struct iav_h26x_drop_frame {
u32 repeat_enable : 1; /*!< Enable repeat drop frame pattern */
u32 reserved0 : 15;
u32 drop_num : 8; /*!< Specify the dropped frame number to repeat */
u32 reserved1 : 8;
};
struct iav_mjpeg_drop_frame {
u32 repeat_enable : 1; /*!< Enable repeat trigger frame pattern */
u32 reserved0 : 15;
u32 drop_num : 8; /*!< Specify the dropped frame number to repeat */
u32 reserved1 : 8;
};
struct iav_trigger_frame {
u32 trigger_frame_enable : 1; /*!< Enable trigger frame */
u32 repeat_enable : 1; /*!< Enable repeat encode frame pattern */
u32 reserved0 : 14;
u32 trigger_num : 8; /*!< Specify the trigger encode frame number to repeat */
u32 reserved1 : 8;
};
struct iav_h26x_cu_split {
u32 disable_cu8 : 1; /*!< Disable CU8 partition, default is 0 */
u32 disable_cu16 : 1; /*!< Disable CU16 partition, default is 0 */
u32 cu8_bias_level : 4; /*!< Specify the bias level for CU8 partition, from 0~6 */
u32 cu16_bias_level : 4; /*!< Specify the bias level for CU16 partition, from 0~6 */
u32 cu32_bias_level : 4; /*!< Specify the bias level for CU32 partition, from 0~6 */
u32 reserved : 18;
};
struct iav_h26x_sar {
u16 sar_width; /*!< Specify customized SAR width */
u16 sar_height; /*!< Specify customized SAR height */
};
struct iav_custom_sei_cfg {
u32 stream_id : 8; /*!< Stream ID */
u32 enable : 1; /*!< Enable insert custom sei. */
u32 insert_I_only : 1; /*!< Enable insert custom sei on I frame only. */
u32 repeat: 1; /*!< Enable repeat last custom sei data. */
u32 dynamic_size_enable: 1; /*!< Enable run time change custom sei payload size, only support PTS frame sync. */
u32 data_size : 16; /*!< Specify the custom sei user data size in bytes */
u32 reserved : 4;
u32 dsp_pts; /*!< Specify the PTS of synchronized frame to apply stream sync of custom sei insertion. */
u32 data_offset; /*!< The offset of the custom sei buffer relative to the memory part of custom sei. @b Read @b Only */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum {
IAV_ONE_BITS_INFO_PER_TILE = 0, /*!< 0 */
IAV_ONE_BITS_INFO_PER_FRAME = 255, /*!< 255 */
};
enum iav_streamcfg_id {
/* Stream config for H264 & H265 & MJPEG (0x0000 ~ 0x0FFF) */
IAV_STMCFG_FORMAT = 0x0000, /*!< 0x0000, Stream config for H264 & H265 & MJPEG (0x0000 ~ 0x0FFF) */
IAV_STMCFG_FPS = 0x0001, /*!< 0x0001 */
IAV_STMCFG_OFFSET = 0x0002, /*!< 0x0002 */
IAV_STMCFG_CHROMA = 0x0003, /*!< 0x0003 */
IAV_STMCFG_DUMMY_LATENCY = 0x0004, /*!< 0x0004 */
IAV_STMCFG_OVERLAY = 0x0005, /*!< 0x0005 */
IAV_STMCFG_FLIP = 0x0006, /*!< 0x0006 */
IAV_STMCFG_MANUAL_ARM_PTS = 0x0007, /*!< 0x0007 */
IAV_STMCFG_FRAME_TRIGGER = 0x0008, /*!< 0x0008 */
IAV_STMCFG_BLUR = 0x0009, /*!< 0x0009 */
IAV_STMCFG_CUSTOM_SEI = 0x000A, /*!< 0x000A */
IAV_STMCFG_YUV_REMAP = 0x000B, /*!< 0x000B */
IAV_STMCFG_NUM = 0x000C, /*!< 0x000C */
IAV_STMCFG_FIRST = IAV_STMCFG_FORMAT, /*!< IAV_STMCFG_FORMAT */
IAV_STMCFG_LAST = IAV_STMCFG_NUM, /*!< IAV_STMCFG_NUM */
/* H264 config (0x1000 ~ 0x1FFF) */
IAV_H264_CFG_GOP = 0x1000, /*!< 0x1000, H264 config (0x1000 ~ 0x1FFF) */
IAV_H264_CFG_BITRATE = 0x1001, /*!< 0x1001 */
IAV_H264_CFG_FORCE_IDR = 0x1002, /*!< 0x1002 */
IAV_H264_CFG_QP_LIMIT = 0x1003, /*!< 0x1003 */
IAV_H264_CFG_ENC_PARAM = 0x1004, /*!< 0x1004 */
IAV_H264_CFG_QP_ROI = 0x1005, /*!< 0x1005 */
IAV_H264_CFG_ZMV_THRESHOLD = 0x1006, /*!< 0x1006 (obsolete) */
IAV_H264_CFG_FORCE_FAST_SEEK = 0x1007, /*!< 0x1007 */
IAV_H264_CFG_FRAME_DROP = 0x1008, /*!< 0x1008 */
IAV_H264_CFG_RC_STRATEGY = 0x1009, /*!< 0x1009 */
IAV_H264_CFG_SLICE = 0x100A, /*!< 0x100A */
IAV_H264_CFG_STATIS = 0x100B, /*!< 0x100B */
IAV_H264_CFG_FORCE_PSKIP = 0x100C, /*!< 0x100C */
IAV_H264_CFG_SAR = 0x100D, /*!< 0x100D */
IAV_H264_CFG_WEIGHTED_PRED = 0x100E, /*!< 0x100E */
IAV_H264_CFG_FAST_SEEK_INTERVAL = 0x100F, /*!< 0x100F */
IAV_H264_CFG_SKIP_STRENGTH = 0x1010, /*!< 0x1010 */
IAV_H264_CFG_ZMV_THRESHOLD_INFO = 0x1011, /*!< 0x1011 (obsolete) */
IAV_H264_CFG_CHROMA_QP_OFFSET = 0x1012, /*!< 0x1012 */
IAV_H264_CFG_ONE_FRM_QP_OFFSET = 0x1013, /*!< 0x1013 */
IAV_H264_CFG_QP_SMOOTH = 0x1014, /*!< 0x1014 */
IAV_H264_CFG_NUM = 0x1015, /*!< 0x1015 */
IAV_H264_CFG_FIRST = IAV_H264_CFG_GOP, /*!< IAV_H264_CFG_GOP */
IAV_H264_CFG_LAST = IAV_H264_CFG_NUM, /*!< IAV_H264_CFG_NUM */
/* MJPEG config (0x2000 ~ 0x2FFF) */
IAV_MJPEG_CFG_QUALITY = 0x2000, /*!< 0x2000, MJPEG config (0x2000 ~ 0x2FFF) */
IAV_MJPEG_CFG_FRAME_DROP = 0x2001, /*!< 0x2001 */
IAV_MJPEG_CFG_NUM = 0x2002, /*!< 0x2002 */
IAV_MJPEG_CFG_FIRST = IAV_MJPEG_CFG_QUALITY, /*!< IAV_MJPEG_CFG_QUALITY */
IAV_MJPEG_CFG_LAST = IAV_MJPEG_CFG_NUM, /*!< IAV_MJPEG_CFG_NUM */
/* H265 config (0x3000 ~ 0x3FFF) */
IAV_H265_CFG_GOP = 0x3000, /*!< 0x3000, H265 config (0x3000 ~ 0x3FFF) */
IAV_H265_CFG_BITRATE = 0x3001, /*!< 0x3001 */
IAV_H265_CFG_FORCE_IDR = 0x3002, /*!< 0x3002 */
IAV_H265_CFG_QP_LIMIT = 0x3003, /*!< 0x3003 */
IAV_H265_CFG_ENC_PARAM = 0x3004, /*!< 0x3004 */
IAV_H265_CFG_QP_ROI = 0x3005, /*!< 0x3005 */
IAV_H265_CFG_ZMV_THRESHOLD = 0x3006, /*!< 0x3006 */
IAV_H265_CFG_FORCE_FAST_SEEK = 0x3007, /*!< 0x3007 */
IAV_H265_CFG_FRAME_DROP = 0x3008, /*!< 0x3008 */
IAV_H265_CFG_RC_STRATEGY = 0x3009, /*!< 0x3009 */
IAV_H265_CFG_SLICE = 0x300A, /*!< 0x300A */
IAV_H265_CFG_MD_CAT_LUT = 0x300B, /*!< 0x300B */
IAV_H265_CFG_FORCE_PSKIP = 0x300C, /*!< 0x300C */
IAV_H265_CFG_SAR = 0x300D, /*!< 0x300D */
IAV_H265_CFG_WEIGHTED_PRED = 0x300E, /*!< 0x300E */
IAV_H265_CFG_FAST_SEEK_INTERVAL = 0x300F, /*!< 0x300F */
IAV_H265_CFG_SKIP_STRENGTH = 0x3010, /*!< 0x3010 */
IAV_H265_CFG_CU_SPLIT = 0x3011, /*!< 0x3011 */
IAV_H265_CFG_CHROMA_QP_OFFSET = 0x3012, /*!< 0x3012 */
IAV_H265_CFG_ONE_FRM_QP_OFFSET = 0x3013, /*!< 0x3013 */
IAV_H265_CFG_QP_SMOOTH = 0x3014, /*!< 0x3014 */
IAV_H265_CFG_NUM = 0x3015, /*!< 0x3015 */
IAV_H265_CFG_FIRST = IAV_H265_CFG_GOP, /*!< IAV_H265_CFG_GOP */
IAV_H265_CFG_LAST = IAV_H265_CFG_NUM, /*!< IAV_H265_CFG_NUM */
};
enum iav_canvas_sync_cfg_id {
IAV_CANVAS_SYNC_CFG_BLUR = 0x0000, /*!< 0x0000 */
IAV_CANVAS_SYNC_CFG_OVERLAY = 0x0001, /*!< 0x0001 */
IAV_CANVAS_SYNC_CFG_NUM = 0x0002, /*!< 0x0002 */
IAV_CANVAS_SYNC_CFG_FIRST = IAV_CANVAS_SYNC_CFG_BLUR, /*!< IAV_CANVAS_SYNC_CFG_BLUR */
IAV_CANVAS_SYNC_CFG_LAST = IAV_CANVAS_SYNC_CFG_NUM, /*!< IAV_CANVAS_SYNC_CFG_NUM */
};
enum roi_cat_type {
ROI_CAT_MIN = 0, /*!< 0 */
ROI_CAT_MAX = 7, /*!< 7 */
};
enum iav_h264_profile {
H264_PROFILE_MAIN = 1, /*!< 1 */
H264_PROFILE_HIGH = 2, /*!< 2 */
H264_PROFILE_NUM = 3, /*!< 3 */
H264_PROFILE_FIRST = H264_PROFILE_MAIN, /*!< H264_PROFILE_MAIN */
H264_PROFILE_LAST = H264_PROFILE_NUM, /*!< H264_PROFILE_NUM */
};
enum iav_h264_au_type {
H264_NO_AUD_NO_SEI = 0, /*!< 0 */
H264_AUD_BEFORE_SPS_WITH_SEI = 1, /*!< 1 */
H264_AUD_AFTER_SPS_WITH_SEI = 2, /*!< 2 */
H264_NO_AUD_WITH_SEI = 3, /*!< 3 */
H264_NO_AUD_ONLY_SPS_WITH_SEI = 4, /*!< 4 */
H264_AU_TYPE_NUM = 5, /*!< 5 */
};
enum iav_h264_aqp_type {
H264_AQP_TYPE_DEFAULT = 0, /*!< 0, Default option in internal RC. */
H264_AQP_TYPE_FRAME_QP = 1, /*!< 1, Frame QP for frame size decision. */
H264_AQP_TYPE_MB_QP = 2, /*!< 2, MB QP for frame size decision. */
H264_AQP_TYPE_NUM = 3, /*!< 3 */
};
enum iav_ltr_num_log2 {
IAV_LTR_NUM_LOG2_MIN = 1, /*!< 1 */
IAV_LTR_NUM_LOG2_MAX = 8, /*!< 8 */
};
enum iav_ltr_type {
IAV_LTR_TYPE_SINGLE = 1, /*!< 1 */
IAV_LTR_TYPE_TWO = 2, /*!< 2 */
IAV_LTR_TYPE_NUM = IAV_LTR_TYPE_TWO, /*!< IAV_LTR_TYPE_TWO */
};
enum iav_two_ltr_mode {
IAV_TWO_LTR_FAST_SEEK = 0, /*!< 0 */
IAV_TWO_LTR_PREV_PREV = 1, /*!< 1 */
IAV_TWO_LTR_MODE_NUM = 2, /*!< 2 */
};
enum iav_gop_model {
IAV_GOP_SIMPLE = 0, /*!< 0, simpe GOP (I & P frames), MPEG2 alike */
IAV_GOP_ADVANCED = 1, /*!< 1, advanced GOP (obsolete) */
IAV_GOP_SVCT_2 = 2, /*!< 2, 2 level SVCT*/
IAV_GOP_SVCT_3 = 3, /*!< 3, 3 level SVCT */
IAV_GOP_SVCT_4 = 4, /*!< 4, 4 level SVCT */
IAV_GOP_FAST_SEEK = 5, /*!< 5, fast seek GOP */
IAV_GOP_2_REF = 6, /*!< 6, 2 ref GOP */
IAV_GOP_FAST_SEEK_2_REF = 7, /*!< 7, 2 ref with fast seek GOP */
IAV_GOP_NON_REF_P = 8, /*!< 8, all P refers from I. App can drop P anytime from the GOP.
This GOP enable fast reverse play. */
};
enum iav_bitrate_control_params {
/* QP limit parameters */
H264_AQP_MAX = 4, /*!< 4, QP limit parameters */
H264_QP_MAX = 51, /*!< 51 */
H264_QP_MIN = 0, /*!< 0 */
H264_I_QP_REDUCE_MAX = 10, /*!< 10 */
H264_I_QP_REDUCE_MIN = 1, /*!< 1 */
H264_P_QP_REDUCE_MAX = 5, /*!< 5 */
H264_P_QP_REDUCE_MIN = 1, /*!< 1 */
H264_B_QP_REDUCE_MAX = 5, /*!< 5 */
H264_B_QP_REDUCE_MIN = 0, /*!< 0 */
H264_C_QP_REDUCE_MAX = 5, /*!< 5 */
H264_C_QP_REDUCE_MIN = 0, /*!< 0 */
H264_Q_QP_REDUCE_MAX = 10, /*!< 10 */
H264_Q_QP_REDUCE_MIN = 1, /*!< 1 */
/* skip frame flag */
H264_WITHOUT_FRAME_DROP = 0, /*!< 0, skip frame flag */
H264_WITH_FRAME_DROP = 6, /*!< 6 */
H264_LOG_Q_NUM_MINUS_1_MAX = 4, /*!< 4 */
H264_I_SIZE_KB_MAX = 8192, /*!< 8192 */
/* cbr stable br adjust */
H264_CBR_STABLE_BR_ADJUST_MIN = 0, /*!< 0, cbr stable br adjust */
H264_CBR_STABLE_BR_ADJUST_MAX = 10, /*!< 10 */
/* ZMV threshold parameters */
H264_ZMV_THRESHOLD_QP_OFFSET_MIN = -51, /*!< -51 */
H264_ZMV_THRESHOLD_QP_OFFSET_MAX = 51, /*!< 51 */
/* chroma qp offset parameters */
H264_CHROMA_QP_OFFSET_MIN = -12, /*!< -12 */
H264_CHROMA_QP_OFFSET_MAX = 12, /*!< 12 */
/* one frame qp offset parameters */
H264_ONE_FRM_QP_OFFSET_MIN = -51, /*!< -51 */
H264_ONE_FRM_QP_OFFSET_MAX = 51, /*!< 51 */
/* intra refresh cycle parameters */
H264_INTRA_REFRESH_CYCLE_MIN = 0, /*!< 0 */
H264_INTRA_REFRESH_CYCLE_MAX = 60, /*!< 60 */
};
enum {
/* bitrate control */
IAV_BRC_CBR = 1, /*!< 1. It's OBSOLETE. */
IAV_BRC_PCBR = 2, /*!< 2. It's OBSOLETE. */
IAV_BRC_VBR = 3, /*!< 3. It's OBSOLETE. */
IAV_BRC_SCBR = 4, /*!< 4, smart CBR */
IAV_BRC_SVBR = 5, /*!< 5. It's OBSOLETE. */
};
enum {
WP_FOR_NONE = 0, /*!< 0 */
WP_FOR_P = 1, /*!< 1 */
WP_FOR_B = 2, /*!< 2 */
WP_FOR_PB = 3, /*!< 3 */
WP_MODE_NUM, /*!< 4 */
WP_MODE_FIRST = WP_FOR_NONE, /*!< WP_FOR_NONE */
WP_MODE_LAST = WP_MODE_NUM, /*!< WP_MODE_NUM */
};
enum {
H26X_LEVEL_IDC_AUTO = 0,
H26X_LEVEL_IDC_11 = 11,
H26X_LEVEL_IDC_12 = 12,
H26X_LEVEL_IDC_13 = 13,
H26X_LEVEL_IDC_20 = 20,
H26X_LEVEL_IDC_21 = 21,
H26X_LEVEL_IDC_22 = 22,
H26X_LEVEL_IDC_30 = 30,
H26X_LEVEL_IDC_31 = 31,
H26X_LEVEL_IDC_32 = 32,
H26X_LEVEL_IDC_40 = 40,
H26X_LEVEL_IDC_41 = 41,
H26X_LEVEL_IDC_42 = 42,
H26X_LEVEL_IDC_50 = 50,
H26X_LEVEL_IDC_51 = 51,
H26X_LEVEL_IDC_52 = 52,
H26X_LEVEL_IDC_60 = 60,
H26X_LEVEL_IDC_61 = 61,
H26X_LEVEL_IDC_62 = 62,
};
#define MAX_NUM_OVERLAY_AREA (16)
#define MAX_NUM_FAST_OVERLAY_AREA (2)
#define OVERLAY_WIN_ALIGN (4)
#if defined(AMBA_SOC_CV5) || defined(AMBA_SOC_CV52)
#define OVERLAY_WIDTH_ALIGN (4)
#define OVERLAY_HEIGHT_ALIGN (4)
#define OVERLAY_X_OFFSET_ALIGN (2)
#define OVERLAY_Y_OFFSET_ALIGN (4)
#else
#define OVERLAY_WIDTH_ALIGN (4)
#define OVERLAY_HEIGHT_ALIGN (2)
#define OVERLAY_X_OFFSET_ALIGN (2)
#define OVERLAY_Y_OFFSET_ALIGN (2)
#endif
#if defined(AMBA_SOC_CV5) || defined(AMBA_SOC_CV52) || defined(AMBA_SOC_N1)
#define OVERLAY_BUF_WIDTH_ALIGN (OVERLAY_WIDTH_ALIGN)
#else
#define OVERLAY_BUF_WIDTH_ALIGN (32)
#endif
/*!< overlay_pitch = ROUND_UP(ROUND_UP(overlay_width, OVERLAY_BUF_WIDTH_ALIGN) * byte_per_pixel, OVERLAY_BUF_PITCH_ALIGN) */
#define OVERLAY_BUF_PITCH_ALIGN (IAV_DSP_BUF_PITCH_ALIGN)
enum iav_blur_type {
IAV_BLUR_TYPE_PM = 0,
IAV_BLUR_TYPE_SMOOTH,
IAV_BLUR_TYPE_NUM,
};
#ifdef CONFIG_AMBVIDEO_CV5X_LEGACY
#define MAX_NUM_BLUR_AREA (8) /*!< Max blur area number per stream. */
#else
#define MAX_NUM_BLUR_AREA (64) /*!< Max blur area number per stream. */
#endif
#define MAX_NUM_BLUR_COLOR (16)
#define MAX_BLUR_COEFF_BLOCKY (2)
#define MAX_BLUR_COEFF_SMOOTH (3)
#define MIN_BLUR_STRENGTH (0)
#define MAX_BLUR_STRENGTH (3)
#define MIN_BLUR_WIDTH (8)
#define BLUR_WIDTH_ALIGN (4)
#define BLUR_HEIGHT_ALIGN (2)
#define BLUR_OFFSET_ALIGN (2)
#define MAX_NUM_YUV_REMAP_AREA (MAX_NUM_OVERLAY_AREA)
#define YUV_REMAP_WIDTH_ALIGN (OVERLAY_WIDTH_ALIGN)
#define YUV_REMAP_HEIGHT_ALIGN (OVERLAY_HEIGHT_ALIGN)
#define YUV_REMAP_X_OFFSET_ALIGN (OVERLAY_X_OFFSET_ALIGN)
#define YUV_REMAP_Y_OFFSET_ALIGN (OVERLAY_Y_OFFSET_ALIGN)
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_overlay_area {
u16 enable : 1; /*!< 0: Disable; 1: Enable */
u16 blend_skip_type : 2; /*!< 0: Enable y&uv blend; 1: Skip y blend; 2: Skip uv blend.*/
u16 reserved0 : 13;
u16 start_x; /*!< Offset x of the overlay area */
u16 start_y; /*!< Offset y of the overlay area */
u16 width; /*!< Width of the overlay area */
u16 pitch; /*!< Pitch of the overlay area */
u16 height; /*!< Height of the overlay area */
u32 total_size; /*!< Total byte size of the overlay area */
unsigned long clut_addr_offset; /*!< CLUT address for the overlay area */
unsigned long data_addr_offset; /*!< Overlay data buffer (without CLUT) */
};
struct iav_overlay_insert {
u32 id; /*!< Stream ID or Canvas ID, decided by id_for_canvas flag. */
u32 enable: 1; /*!< Flag to enable / disable overlay insertion */
u32 osd_insert_always: 1; /*!< Flag to insert overlay all the time no matter the encoding of next frame is started or not. */
u32 osd_num_regions : 5 ; /*!< osd num region */
u32 id_for_canvas : 1; /*!< Flag to set id for 1: canvas id or 0: stream id. */
u32 reserved : 24; /*!< reserved */
struct iav_overlay_area area[MAX_NUM_OVERLAY_AREA]; /*!< Parameters for each overlay area */
};
struct iav_blur_area {
u32 enable : 1; /*!< 0: Disable; 1: Enable */
u32 strength : 3; /*!< Blur strength, the larger the more heavily blurred */
u32 use_arb_blur : 1; /*!< Use user customized blur data which is specified through arb_blur_offset */
u32 is_blocky : 1; /* 0 disable blocky effect, 1 enable blocky effect */
u32 coeff : 2; /*!< blur coefficient. Allow different coeff on the same frame.
Valid range is [0, 3] when is_blocky is 0, and [0, 2] when is_blocky is 1. 0:weakest blur. */
u32 color_idx : 4; /*!< Blur color index of the colors specified through IAV_IOC_SET_BLUR_COLOR. It is only valid when colored_blur = 1. */
u32 color_enable : 1; /*!< Flag to enable / disable blur color. 0: Disable. 1: Enable. */
u32 reserved0 : 19;
u16 start_x; /*!< Offset x of the blur area */
u16 start_y; /*!< Offset y of the blur area */
u16 width; /*!< Width of the blur area */
u16 height; /*!< Height of the blur area */
u16 arb_blur_pitch; /*!< Arbitrary blur data pitch. Used only when use_arb_blur is enabled */
u16 reserved1;
u32 arb_blur_offset; /*!< Arbitrary blur data offset. Used only when use_arb_blur is enabled */
};
struct iav_blur_insert {
union {
u8 stream_id; /*!< Stream ID */
u8 canvas_id; /*!< Canvas ID */
};
u8 enable : 1; /*!< Flag to enable/disable blur insertion */
u8 blur_num_regions : 7; /*!< blur num regions */
u8 type : 2; /*!< Blur type. 0(default): normal blur (pm blur). 1: smooth blur, it can be used
to remove non-useful high frequency details (more smooth), to save bit-rate when encoding. */
u8 id_for_canvas : 1; /*!< Flag to set id for 1: canvas id, 0: stream id. */
u8 reserved0 : 5;
u8 reserved1;
struct iav_blur_area area[MAX_NUM_BLUR_AREA]; /*!< Parameters for each blur area */
};
struct iav_blur_color {
u32 color_idx_map; /*!< the idx map of configured blur colors */
u8 U[MAX_NUM_BLUR_COLOR]; /*!< chroma U value */
u8 V[MAX_NUM_BLUR_COLOR]; /*!< chroma V value */
u32 reserved[3];
};
struct iav_yuv_remap_area {
u16 enable : 1; /*!< 0: Disable; 1: Enable */
u16 yuv_remap_en : 2; /*!< Enable YUV remap; 0: Enable Y & UV remap; 1: Enable only UV remap; 2: Enable only Y remap. */
u16 reserved : 13;
u16 start_x; /*!< Offset x of the YUV remap area */
u16 start_y; /*!< Offset y of the YUV remap area */
u16 width; /*!< Width of the YUV remap area */
u16 height; /*!< Height of the YUV remap area */
u16 reserved1;
unsigned long clut_addr_offset; /*!< CLUT address for the YUV remap area */
};
struct iav_yuv_remap {
u32 id; /*!< Stream ID */
u32 enable: 1; /*!< Flag to enable / disable YUV remap insertion */
u32 insert_always: 1; /*!< Flag to insert YUV remap all the time no matter the encoding of next frame is started or not. */
u32 remap_num_regions : 5 ; /*!< YUV remap num region */
u32 reserved : 25; /*!< reserved */
struct iav_yuv_remap_area area[MAX_NUM_YUV_REMAP_AREA]; /*!< Parameters for each YUV remap area */
};
struct iav_fusion_info
{
u32 chan_id : 8; /*!< Channel ID */
u32 pass_id : 8; /*!< Pass ID */
u32 buf_id : 8; /*!< Source Buffer ID */
u32 reserved : 8;
u32 buffer_offset_x : 16; /*!< Offset x of fusion buffer in the source buffer */
u32 buffer_offset_y : 16; /*!< Offset y of fusion buffer in the source buffer */
};
struct iav_fusion_cfg
{
u32 chan_id : 8; /*!< Fusion channel ID. */
u32 canvas_id : 8; /*!< Fusion output canvas ID. */
u32 reserved : 16;
struct iav_window fusion_win; /*!< Fusion blend window. */
struct iav_fusion_info src0_info; /*!< Fusion input source 0 buffer info */
struct iav_fusion_info src1_info; /*!< Fusion input source 1 buffer info */
struct iav_fusion_info out_info; /*!< Fusion output buffer info */
};
struct iav_zmv_threshold_info {
u8 enable; /*!< Flag to enable ZMV threshold info */
s8 qp_offset; /*!< QP offset for zero motion vector MB, valid range is [-51, 51] */
u8 reserved[2];
};
struct iav_stream_cfg {
u32 id; /*!< Stream ID */
enum iav_streamcfg_id cid; /*!< Stream configured ID, @sa iav_streamcfg_id */
union {
struct iav_stream_format format; /*!< Stream format @sa iav_stream_format */
struct iav_stream_fps fps; /*!< Stream fps @sa iav_stream_fps */
struct iav_offset enc_offset; /*!< Stream offset on canvas */
enum iav_chroma_format chroma; /*!< Stream chroma format @sa iav_chroma_format */
u32 stream_dummy_latency; /*!< Stream dummy latency. It's used by stream sync mechanism. */
u32 mv_threshold; /*!< MV threshold for bitrate control */
struct iav_overlay_insert overlay; /*!< overlay information. It's used by frame sync mechanism for application
to synchronize overlay with the speicfied frame content. */
struct iav_stream_flip flip; /*< Stream flip information. */
struct iav_blur_insert blur; /*!< blur information. It's used by frame sync mechanism for application
to synchronize blur with the speicfied frame content. */
struct iav_yuv_remap yuv_remap; /*!< yuv_remap information. It's used by frame sync mechanism for application
to synchronize yuv remap with the speicfied frame content. */
struct iav_trigger_frame trigger_frame; /*!< Specify the trigger frame number to encode */
struct iav_h26x_gop h264_gop;
struct iav_bitrate h264_rc;
struct iav_rc_strategy h264_rc_strategy;
struct iav_qpmatrix h264_roi;
struct iav_h26x_enc_param h264_enc;
struct iav_h26x_slice h264_slice;
struct iav_h26x_pskip h264_pskip;
struct iav_h26x_drop_frame h264_drop_frame;
int h264_force_idr; /*!< Flag for force IDR */
u32 h264_force_fast_seek; /*!< Flag for force fast seek frame insertion */
u32 h264_fast_seek_interval; /*!< Flag for fast seek interval */
u32 h264_statis; /*!< H.264 MV dump flag */
u32 h264_skip_strength; /*!< Skip strength for h.264, default is 2. */
int h264_chroma_qp_offset; /*!< Set H.264 chroma qp offset */
int h264_one_frm_qp_offset; /*!< Set H.264 one frame qp offset */
int h264_qp_smooth_enable; /*!< Set H.264 qp smooth */
struct iav_h26x_sar h264_sar; /*!< Customized H.264 stream aspect ratio */
struct iav_h26x_weighted_pred h264_wp; /*!< Weighted predition info */
struct iav_zmv_threshold_info h264_zmv_threshold; /*!< Zero motion vector threshold info */
u32 mjpeg_quality; /*!< Quality value for MJPEG stream */
struct iav_mjpeg_drop_frame mjpeg_drop_frame; /*!< Frame drop for mjpeg */
/* H265 shares same structure with H264 */
struct iav_h26x_gop h265_gop;
struct iav_bitrate h265_rc;
struct iav_rc_strategy h265_rc_strategy;
struct iav_qpmatrix h265_roi;
struct iav_h26x_enc_param h265_enc;
struct iav_h26x_slice h265_slice;
struct iav_h26x_pskip h265_pskip;
struct iav_h26x_drop_frame h265_drop_frame;
struct iav_h26x_cu_split h265_cu_split;
int h265_force_idr; /*!< Flag for force IDR */
u32 h265_force_fast_seek; /*!< Flag for force fast seek frame insertion */
u32 h265_fast_seek_interval; /*!< Flag for fast seek interval */
u32 h265_skip_strength; /*!< Skip strength for h.265, default is 2. */
u8 h265_md_cat_lut[MD_CAT_MAX_NUM]; /*!< H.265 MD category mapping look up table */
int h265_chroma_qp_offset; /*!< Set H.265 chroma qp offset */
int h265_one_frm_qp_offset; /*!< Set H.265 one frame qp offset */
int h265_qp_smooth_enable; /*!< Set H.265 qp smooth */
struct iav_h26x_sar h265_sar; /*!< Customized H.265 stream aspect ratio */
struct iav_h26x_weighted_pred h265_wp;
struct iav_custom_sei_cfg custom_sei;
} arg; /*!< The stream configuration items */
u32 dsp_pts; /*!< The DSP PTS for the stream configurations */
u32 strm_sync_type : 3; /*!< Select frame sync, or stream sync */
u32 manual_arm_pts_enable : 1; /*!< Manual arm_pts enable */
u32 reserved : 28;
};
struct iav_canvas_sync_cfg {
u32 id; /*!< Canvas ID */
enum iav_canvas_sync_cfg_id cid; /*!< Canvas sync configured ID, @sa iav_canvas_sync_cfg_id */
union {
struct iav_blur_insert blur; /*!< blur information. It's used by frame sync mechanism for application
to synchronize blur with the speicfied frame content. */
struct iav_overlay_insert overlay; /*!< overlay information. It's used by frame sync mechanism for application
to synchronize overlay with the speicfied frame content. */
} arg; /*!< The canvas sync configuration items */
};
struct iav_pic_info {
u32 rate; /*!< Stream fps rate info */
u32 scale; /*!< Stream fps scale into */
u16 width; /*!< Stream width */
u16 height; /*!< Stream height */
};
struct iav_h26x_cfg {
u32 id; /*!< Stream ID */
u32 gop_structure : 8; /*!< @sa iav_gop_model */
u32 M : 8; /*!< Number of pictures between reference P pictures */
u32 N : 16; /*!< Number of pictures between reference I pictures, should be no larger than 4095 */
u32 idr_interval : 8; /*!< Indicate the number of GOP's after which an IDR picture should happen */
u32 profile : 8; /*!< This field specifies the profile level for stream configuration. The default is the
high profile for H264 and main profile for H265. 1: Main profile. 2: High profile. */
u32 au_type : 8; /*!< This field specifies the NAL unit structure.
0: No AUD, no SEI header info
1: Add AUD before SPS, PPS, with SEI in the end
2: Add AUD after SPS, PPS, with SEI in the end
3: IDR: AUD -> SPS -> BPSEI & PTSEI, P: AUD -> SPS & PPS -> PTSEI
4: no AUD, SPS/PPS -> SEI */
u32 chroma_format : 8; /*!< Chroma format */
u32 cpb_buf_idc : 8; /*!< CPB buffer size indicator. 0 indicates using a buffer size that
matches the profile and level which are based on the encoding size. */
u32 is_update_N_to_next_GOP : 1; /*!< Flag to update GOP length to next
GOP (obsolete, N is always updated in current GOP but not next GOP) */
u32 scalelist_opt : 2; /*!< scalelist option, 0: No scaling list,
1: default scaling list in default_binary, 2: custom scaling list */
int chroma_qp_offset : 5; /* chroma qp offset */
int one_frm_qp_offset : 8; /*!< QP offset on specific frames, range from -51 to 51 */
u32 intra_bias_override_usr1 : 1; /*!< User1 intra bias mode, 0: add, 1: override */
u32 direct_bias_override_usr1 : 1; /*!< User1 direct bias mode, 0: add, 1: override */
u32 intra_bias_override_usr2 : 1; /*!< User2 intra bias mode, 0: add, 1: override */
u32 direct_bias_override_usr2 : 1; /*!< User2 direct bias mode, 0: add, 1: override */
u32 h26x_scalelist_strength : 3; /*!< This field specifies the h26x scalelist strength level (@ref IAV_H26X_SCALELIST_STRENGTH).
Default is 1. 0: off, 1: low strength, 2: medium strength, 3: high strength */
u32 qp_smooth_enable : 1; /*!< Flag to enable QP smooth to achieve more stable bitrate */
u32 cpb_user_size; /*!< This field specifies the CPB buffer size */
u32 en_panic_rc : 2; /*!< Flag for panic mode of RC */
u32 cpb_cmp_idc : 2; /*!< Flag for CPB settings */
u32 fast_rc_idc : 4; /*!< Flag for fast RC mode (obsolete) */
u32 mv_threshold : 1; /*!< Motion vector threshold */
u32 long_start_code : 1;/*!< Flag for long start code */
u32 dblk_custom_flag : 1; /*!< Flag for dblk */
u32 two_ltrs_mode : 1; /*!< 0: two long term + fast seek; 1: two long term + prev prev q */
u32 ltrs_type: 2; /*!< Type of long term references. Default is 0.
0: No long term ref frame
1: 1 long term ref frame
2: 2 long term ref frames. */
u32 zmv_enable_flag : 1; /*!< Flag to enable/disable ZMV feature */
u32 two_str : 1; /*!< 0: one long term + one short term; 1: two short term. Only valid when GOP is IAV_GOP_2_REF. */
u32 log2_num_ltrp_per_gop : 8; /*!< Number of long-term reference picture in a GoP (obsolete) */
u32 fast_seek_intvl : 8; /*!< The fast seek interval for long term frames */
u16 user1_intra_bias; /*!< The intra bias for user class 1, range from 0 to 65535 */
u16 user1_direct_bias; /*!< The direct bias for user class 1, range from 0 to 65535 */
u16 user2_intra_bias; /*!< The intra bias for user class 2, range from 0 to 65535 */
u16 user2_direct_bias; /*!< The direct bias for user class 2, range from 0 to 65535 */
s32 deblocking_filter_alpha : 4; /*!< The deblocking filter range is -6 to 6 */
s32 deblocking_filter_beta : 4; /*!< The deblocking filter range is -6 to 6 */
u32 deblocking_filter_enable : 2;/*!< Flag for deblocking filter */
u32 aqp_type : 2; /*!< AQP type for frame size decision, @sa iav_h264_aqp_type:
0: Use frame level QP for mode decision and size decision
1: Use frame level QP for mode decision, MB level qp for size decision
2: Use MB level QP for mode decision and size decision */
u32 wp_mode : 2; /*!< Weighted predict mode :
0: Disable WP,
1: WP for P frame,
2: WP for B frame,
3: WP for P&B frame */
u32 custom_nal_ref_idc_type : 2; /*!< 0: default, 1: IPB 320 for simple GOP non fastseek */
u32 intra_refresh_cycle : 7; /*!< Use P frames with intra blocks to replace I frames in non-first GOPs in GOP boundaries.
For these P frames, each contains a fixed size of intra MB or CTB rows from different areas. The intra
refresh cycle ranges from 0~60, 0: disable intra refresh, 1~60: intra refresh cycles. Each area height is
around frame height divided by intra refresh cycle. */
u32 constrained_intra_enable : 1; /*!< Flag for constrained intra prediction: 0: disable (default); 1: enable. */
int zmv_threshold_qp_offset : 8; /*!< QP offset for ZMV, it's only valid when "zmv_enable_flag" is set */
struct iav_pic_info pic_info; /*!< Picture information for decoding (rate / scale) */
u8 level_idc : 8; /*!< H26x level idc setting, the value is 0/11/12/13/20/21/22/30/31/32/40/41/42/51/52/60/61/62, 0: By IAV calculation */
u8 reserved[7];
};
struct iav_mjpeg_cfg {
u32 id; /*!< Stream ID */
u32 chroma_format : 8; /*!< Chroma format, @sa iav_chroma_format */
u32 quality : 8; /*!< 1 ~ 100, 100 is best quality. The bigger quality value,
the larger frame size it is (especially for high mega resolution). */
u32 slice_num : 5; /*!< Slice number for MJPEG multi-slice encoding. */
u32 reserved0 : 11;
u32 restart_interval; /*!< restart interval MB for mjpeg. 0 : handle in ucode. >0 : user specified. */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum iav_warp_params {
/* The *_OFFSET means the offset in the warp memory for one warp area. The default memory unit for warp area is (H/V/ME1_V) */
WARP_AREA_H_OFFSET = 0, /*!< 0 */
WARP_AREA_V_OFFSET = 1, /*!< 1 */
WARP_AREA_ME1_OFFSET = 2, /*!< 2 */
WARP_AREA_VECTOR_NUM = 3, /*!< 3 */
RAW_PADDING_TABLE_IN_BYTES = 4096, /*!< 4096 */
MAX_NUM_WARP_AREAS = 12, /*!< 12, Maximum warp area number from DSP point of view. */
MAX_NUM_WARP_VIEW = 12, /*!< 12, Maximum warp view number from user point of view. */
MAX_GRID_WIDTH = 128, /*!< 128, Maximum grid width (column) for warp vector table. */
MAX_GRID_HEIGHT = 96, /*!< 96, Maximum grid height (row) for warp vector table. */
MAX_WARP_TABLE_SIZE = (MAX_GRID_WIDTH * MAX_GRID_HEIGHT), /*!< MAX_GRID_WIDTH * MAX_GRID_HEIGHT */
MAX_WARP_VECT_PART_SIZE = (MAX_NUM_WARP_AREAS * MAX_WARP_TABLE_SIZE * sizeof(s16) * WARP_AREA_VECTOR_NUM), /*!< MAX_NUM_WARP_AREAS *
MAX_WARP_TABLE_SIZE * sizeof(s16) * WARP_AREA_VECTOR_NUM */
MAX_GRID_WIDTH_LDC = MAX_GRID_WIDTH, /*!< MAX_GRID_WIDTH */
MAX_WARP_TABLE_SIZE_LDC = (MAX_GRID_WIDTH_LDC * MAX_GRID_HEIGHT), /*!< MAX_GRID_WIDTH_LDC * MAX_GRID_HEIGHT */
MAX_ME1_WARP_TABLE_SIZE_LDC = MAX_WARP_TABLE_SIZE_LDC / 16, /*!< (MAX_GRID_WIDTH_LDC/4) * (MAX_GRID_HEIGHT/4) */
MAX_MD_WARP_TABLE_SIZE_LDC = MAX_WARP_TABLE_SIZE_LDC / 256, /*!< (MAX_GRID_WIDTH_LDC/16) * (MAX_GRID_HEIGHT/16) */
MAX_GRID_WIDTH_HKM = 256, /*!< 256. HKM stands for Horizon Keeping Mode (mode 3). Maximum grid width (column) for warp vector table. */
MAX_WARP_TABLE_SIZE_HKM = (MAX_GRID_WIDTH_HKM * MAX_GRID_HEIGHT), /*!< MAX_GRID_WIDTH_HKM * MAX_GRID_HEIGHT */
GRID_SPACING_PIXEL_8 = 0, /*!< 0 */
GRID_SPACING_PIXEL_16 = 1, /*!< 1 */
GRID_SPACING_PIXEL_32 = 2, /*!< 2 */
GRID_SPACING_PIXEL_64 = 3, /*!< 3 */
GRID_SPACING_PIXEL_128 = 4, /*!< 4 */
GRID_SPACING_PIXEL_256 = 5, /*!< 5 */
GRID_SPACING_PIXEL_512 = 6, /*!< 6 */
WARP_AREA_CHANGE = 0, /*!< 0, This is to change the selected warp area configuration on the fly. */
WARP_AREA_UPDATE = 1, /*!< 1, This is to update all warp areas configuration at the same time. */
WARP_AREA_CLEAR = 2, /*!< 2, This is to clear warp for all warp regions. */
WARP_PIPELINE_VH = 0, /*!< 0, Pipeline type: V + H. */
WARP_PIPELINE_HV = 1, /*!< 1, Pipeline type: H + V. */
#if defined(AMBA_SOC_CV75)
MAX_WARP_AREA_WIDTH_NON_STITCH = 1216,
#else
MAX_WARP_AREA_WIDTH_NON_STITCH = 2048,
#endif
MAX_WARP_AREA_WIDTH_STITCH = 4096,
MIN_WARP_AREA_WIDTH = 112,
WARP_IN_X_ALIGN = 16, /*!< 16, This is multi region warp area's input x alignment. */
WARP_IN_Y_ALIGN = 8, /*!< 8, This is multi region warp area's input y alignment. */
WARP_IN_V_ALIGN = 8, /*!< 8, This is multi region warp area's input vertical alignment. */
WARP_HV_IN_H_ALIGN = 16, /*!< 16, This is multi region warp area's input horizontal alignment under H + V pipeline. */
WARP_VH_IN_H_ALIGN = 32, /*!< 32, This is multi region warp area's horizontal alignment of Vwarp input under V + H pipeline. */
WARP_VH_IN_V_ALIGN = 8, /*!< 8, This is multi region warp area's vertical alignment of Vwarp input under V + H pipeline. */
WARP_VH_DMA_IN_H_ALIGN = 16, /*!< 16, This is multi region warp area's horizontal alignment of DMA input (before rotate) under V + H pipeline. */
WARP_OUT_X_ALIGN = 2, /*!< 2, This is multi region warp area's output x alignment. */
WARP_OUT_Y_ALIGN = 2, /*!< 2, This is multi region warp area's output y alignment. */
WARP_OUT_V_ALIGN = 8, /*!< 8, This is multi region warp area's output vertical alignment. */
WARP_OUT_H_ALIGN = 16, /*!< 16, This is multi region warp area's output horizontal alignment. */
WARP_INT_H_ALIGN = 16, /*!< 16, This is multi region warp intermediate buffer horizontal alignment. */
WARP_INT_V_ALIGN = 16, /*!< 16, This is multi region warp intermediate buffer vertical alignment. */
HWARP_PADDING_MAX_FACTOR = 8, /*!< 8, This is max hwarp padding factor for multi region warp area stitching. The actual padding is factor * HWARP_PADDING_UNIT. */
HWARP_PADDING_UNIT = 64, /*!< 64, This is the multiplier of hwarp padding for multi region warp area stitching. The actual padding is factor * HWARP_PADDING_UNIT. */
};
enum lens_warp_reso_type {
LENS_WARP_RES_TYPE_MAIN = 0, /*!< 0, Load horizontal warp + vertical warp for main buffer. */
LENS_WARP_RES_TYPE_MAIN_MONO = LENS_WARP_RES_TYPE_MAIN, /*!< 0, Load align/ldc horizontal warp + align vertical warp FOR MONO channel. */
LENS_WARP_RES_TYPE_ME1 = 1, /*!< 1, Load ME1 vetical warp vector. Should be disabled in fusion mode*/
LENS_WARP_RES_TYPE_MAIN_RGB = 2, /*!< 2, Load RGB horizontal warp + fusion/RGB vertical warp in fusion mode. */
LENS_WARP_RES_TYPE_MD_BC = 3, /*!< 3, Load MD_BC vetical warp vector in fusion mode. */
LENS_WARP_RES_TYPE_NUM = 4,
LENS_WARP_RES_TYPE_FIRST = LENS_WARP_RES_TYPE_MAIN, /*!< LENS_WARP_RES_TYPE_MAIN */
LENS_WARP_RES_TYPE_LAST = LENS_WARP_RES_TYPE_NUM, /*!< LENS_WARP_RES_TYPE_NUM */
};
enum iav_warp_uncorrected_buf_id {
IAV_WARP_PRE_MAIN_BUF = 0, /*!< 0, Premain buffer */
IAV_WARP_PRE_2ND_BUF, /*!< 1, Second buffer from uncorrected pass. */
IAV_WARP_PRE_3RD_BUF, /*!< 2, Third buffer from uncorrected pass. */
IAV_WARP_PRE_4TH_BUF, /*!< 3, Fourth buffer from uncorrected pass. */
IAV_WARP_PRE_BUF_NUM,
};
enum iav_warp_ctrl_id {
IAV_WARP_CTRL_MAIN = 0, /*!< 0, This is to configure multi-region warp area parameters for post main. */
IAV_WARP_CTRL_DPTZ = 1, /*!< 1, This is to configure multi-region warp DPTZ from post main to sub source buffers. */
IAV_WARP_CTRL_ENCOFS = 2, /*!< 2, This is to configure stream encode offset synchronized with warp DPTZ effect. */
IAV_WARP_CTRL_MAX_CFG = 3, /*!< 3, This is to configure max resource for each multi-region warp area. */
IAV_WARP_CTRL_NUM = 4, /*!< 4 */
IAV_WARP_CTRL_FIRST = IAV_WARP_CTRL_MAIN, /*!< IAV_WARP_CTRL_MAIN */
IAV_WARP_CTRL_LAST = IAV_WARP_CTRL_NUM, /*!< IAV_WARP_CTRL_NUM */
};
enum iav_warp_area_rotate_flip {
WARP_AREA_H_FLIP = (1U << 0), /*!< 0x1, Warp area horizontal flip */
WARP_AREA_V_FLIP = (1U << 1), /*!< 0x2, Warp area vertical flip */
WAPR_AREA_ROTATE_CW = (1U << 2), /*!< 0x4, Warp area rotate 90 degrees in clockwise */
WARP_AREA_HV_FLIP = (WARP_AREA_H_FLIP | WARP_AREA_V_FLIP), /*!< 0x3, Warp area rotate 180 degrees */
WAPR_AREA_ROTATE_CCW = (WARP_AREA_H_FLIP | WARP_AREA_V_FLIP | WAPR_AREA_ROTATE_CW), /*!< 0x7, Warp area rotate 90 degrees in counter-clockwise */
};
enum iav_mrd_params {
MAX_MRD_AREA_WIDTH_STITCH = 4096,
MRD_INPUT_WIDTH_DEFAULT = 2048,
MRD_OUTPUT_WIDTH_DEFAULT = 2048,
MAX_NUM_DPTZ_AREAS = 12,
IAV_MULTI_REGION_DPTZ_BUF_NUM = 6,
MIN_REGION_WIDTH_IN_MRD = 352,
MIN_MRD_AREA_WIDTH = 112,
MRD_IN_X_ALIGN = 16, /*!< 16, This is multi region dptz area's input x alignment. */
MRD_IN_Y_ALIGN = 8, /*!< 8, This is multi region dptz area's input y alignment. */
MRD_IN_V_ALIGN = 8, /*!< 8, This is multi region dptz area's input vertical alignment. */
MRD_IN_H_ALIGN = 32, /*!< 32, This is multi region dptz area's input horizontal alignment. */
MRD_OUT_X_ALIGN = 2, /*!< 2, This is multi region dptz area's output x alignment. */
MRD_OUT_Y_ALIGN = 2, /*!< 2, This is multi region dptz area's output y alignment. */
MRD_OUT_V_ALIGN = 2, /*!< 8, This is multi region dptz area's output vertical alignment. */
MRD_OUT_H_ALIGN = 4, /*!< 16, This is multi region dptz area's output horizontal alignment. */
MRD_OUT_X_ALIGN_BURST_TILE = 16, /*!< 16, This is multi region dptz area's output x alignment. */
MRD_OUT_Y_ALIGN_BURST_TILE = 8, /*!< 8, This is multi region dptz area's output y alignment. */
MRD_OUT_V_ALIGN_BURST_TILE = 8, /*!< 8, This is multi region dptz area's output vertical alignment. */
MRD_OUT_H_ALIGN_BURST_TILE = 16, /*!< 16, This is multi region dptz area's output horizontal alignment. */
};
enum iav_idsp_sync_ctrl_id{
IAV_IDSP_SYNC_CTRL_MRD = 0,
IAV_IDSP_SYNC_CTRL_NUM = 1,
IAV_IDSP_SYNC_CTRL_FIRST = IAV_IDSP_SYNC_CTRL_MRD,
IAV_IDSP_SYNC_CTRL_LAST = IAV_IDSP_SYNC_CTRL_NUM,
};
enum iav_multi_region_dptz_ctrl_id{
IAV_MULTI_REGION_DPTZ_CTRL_MAIN = 0,
IAV_MULTI_REGION_DPTZ_CTRL_NUM = 1,
IAV_MULTI_REGION_DPTZ_CTRL_FIRST = IAV_MULTI_REGION_DPTZ_CTRL_MAIN,
IAV_MULTI_REGION_DPTZ_CTRL_LAST = IAV_MULTI_REGION_DPTZ_CTRL_NUM,
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_warp_map {
u8 enable; /*!< Flag to enable / disable warp vector table. */
u8 output_grid_col; /*!< Grid columns */
u8 output_grid_row; /*!< Grid rows */
u8 h_spacing : 4; /*!< H-spacing */
u8 v_spacing : 4; /*!< V-spacing */
u32 reserved;
unsigned long data_addr_offset; /*!< Warp table DRAM offset */
};
struct iav_warp_area {
u8 enable; /*!< Area enable flag */
u8 rotate_flip; /*!< Rotate and flip flag. H-flip : 0x1, V-flip : 0x2, CW-rotate : 0x4, CCW-rotate : 0x7 */
u16 warp_pipeline_type : 3; /*!< pipeline type: 0: V + H; 1: H + V; 2 ~ 7 are reserved for now */
u16 main_yuv_disable : 1; /*!< 0: (default behavior) Writing YUV in main buffer; 1: Disable writing YUV in main buffer*/
u16 idsp_core_cfg_enable : 1; /*!< This field is only available for the SoC with multiple cores, like CV5x/N1/... */
u16 idsp_core_mode : 2; /*!< @sa iav_idsp_core_mode. Only valid when idsp_core_cfg_enable = 1. */
u16 hwarp_padding_factor : 4; /*!< Padding factor for warp area stitching. Valid range 0 ~ HWARP_PADDING_MAX_FACTOR. Actual padding is factor * HWARP_PADDING_UNIT. */
u16 reserved0 : 5;
struct iav_rect input; /*!< Warp area input window */
struct iav_rect output; /*!< Warp area output window */
struct iav_warp_map h_map; /*!< h-warp map */
struct iav_warp_map v_map; /*!< v-warp map */
struct iav_warp_map me1_v_map; /*!< me1-v-warp map */
};
struct iav_warp_main {
u8 keep_dptz[IAV_WARP_DPTZ_BUF_NUM]; /*!< Keep DPTZ attribute for each source buffer output */
u8 area_num_per_view[MAX_NUM_WARP_VIEW]; /*!< Specify the number of warp areas for each warp view. */
struct iav_warp_area area[MAX_NUM_WARP_AREAS]; /*!< Warp area configuration */
};
struct iav_warp_dptz {
u16 buf_id; /*!< Source buffer ID */
u16 area_map; /*!< The bit map of areas to be changed in warp dptz. */
struct iav_rect input[MAX_NUM_WARP_AREAS]; /*!< Input window of each updated area. */
struct iav_rect output[MAX_NUM_WARP_AREAS]; /*!< Output window of each updated area. */
};
struct iav_warp_max_cfg {
u16 max_warp_output_width[MAX_NUM_WARP_AREAS]; /*!< Max output width of each area. */
};
struct iav_warp_ctrl {
enum iav_warp_ctrl_id cid; /*!< Config class ID, @sa iav_warp_ctrl_id */
u16 channel_id; /*!< Channel ID */
u16 warp_area_behavior : 2; /*!< Specify warp area behavior.
0 (@ref WARP_AREA_CHANGE), is to change the selected warp area configuration on the fly.
1 (@ref WARP_AREA_UPDATE). is to update all warp areas configuration at the same time.
2 (@ref WARP_AREA_CLEAR), is to clear all warp areas configuration at the same time. */
/* ISP NN warp, 4x warp table (YUV h/v_map and me1 h/v_map) are required, use another item
* iav_warp_area array from struct iav_warp_main to address me1 h/v_map. */
u16 isp_nn_area_id : 4; /*!< ISP NN pass warp area id. Read-only to Application. */
u16 reserved : 10;
union {
struct iav_warp_main main;
struct iav_warp_dptz dptz;
struct iav_warp_max_cfg max_cfg;
} arg; /*!< Warp configuration */
};
struct iav_multi_region_dptz {
u32 buf_id : 8; /*!< Source buffer ID */
u32 area_map : 24; /*!< The bit map of areas to be changed in multi region dptz. */
struct iav_rect input[MAX_NUM_DPTZ_AREAS]; /*!< Input window of each updated area. */
struct iav_rect output[MAX_NUM_DPTZ_AREAS]; /*!< Output window of each updated area. */
};
struct iav_multi_region_dptz_area {
u8 enable; /*!< Area enable flag */
u8 rotate_flip; /*!< Rotate and flip flag. H-flip : 0x1, V-flip : 0x2, CW-rotate : 0x4, CCW-rotate : 0x7 */
u16 main_yuv_disable : 1; /*!< 0: (default behavior) Writing YUV in main buffer; 1: Disable writing YUV in main buffer*/
u16 idsp_core_cfg_enable : 1; /*!< This field is only available for the SoC with multiple cores, like CV5x/N1/... */
u16 idsp_core_mode : 2; /*!< @sa iav_idsp_core_mode. Only valid when idsp_core_cfg_enable = 1. */
u16 dptz_buf_id_map : 8; /*!< Specify the preview buffer id enabled in the current area. */
u16 reserved0 : 4;
u32 src_chan_id; /*!< Specify the src channel id of this area. Only valid when the src is hier srcbuf. */
u32 src_layer_id; /*!< Specify the src pyramid layer id of this area. Only valid when the src is hier srcbuf. */
struct iav_rect input; /*!< Specify the area input window. */
struct iav_rect output; /*!< Specify the area output window. */
};
struct iav_multi_region_dptz_main {
u8 keep_dptz[IAV_MULTI_REGION_DPTZ_BUF_NUM]; /*!< Keep DPTZ attribute for each source buffer output */
struct iav_multi_region_dptz_area area[MAX_NUM_DPTZ_AREAS]; /*!< Multi region dptz area configuration */
};
struct iav_multi_region_dptz_params {
struct iav_multi_region_dptz_main main;
struct iav_multi_region_dptz dptz[IAV_SRCBUF_NUM];
};
struct iav_multi_region_dptz_ctrl {
enum iav_multi_region_dptz_ctrl_id cid; /*!< Config class ID, @sa iav_multi_region_dptz_ctrl_id */
u32 channel_id : 8; /*!< Channel ID */
u32 reserved : 24;
struct iav_multi_region_dptz_main main;
struct iav_multi_region_dptz dptz[IAV_SRCBUF_NUM];
};
struct iav_blend_warp {
u8 canvas_id; /*!< Input Canvas id */
u8 reserved;
u16 update_area_map; /*!< Bitmap of areas to update blend warp table */
struct iav_warp_map h_map[IAV_BLEND_OVERLAP_AREA_MAX][IAV_BLEND_NUM]; /*!< h-warp map */
u16 extra_overlap[IAV_BLEND_OVERLAP_AREA_MAX][IAV_BLEND_NUM]; /*!< Additional range to perform blend warp. */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum iav_blend_buf {
IAV_BLEND_BUF_Z0 = 0, /*!< 0, blending reference buffer at Z-order 0 */
IAV_BLEND_BUF_Z1 = 1, /*!< 1, blending reference buffer at Z-order 1, also the final blended result buffer */
IAV_BLEND_BUF_Z1_COPY_OUT = 2, /*!< 2, the copy out buffer of Z-order 1 reference buffer */
IAV_BLEND_BUF_NUM = 3, /*!< 3 */
IAV_BLEND_BUF_FIRST = IAV_BLEND_BUF_Z0, /*!< IAV_BLEND_BUF_COPY_OUT */
IAV_BLEND_BUF_LAST = IAV_BLEND_BUF_NUM, /*!< IAV_BLEND_BUF_NUM */
};
enum iav_paddings {
IAV_PADDING_TOP = 0, /*!< 0, top padding */
IAV_PADDING_RIGHT = 1, /*!< 1, right padding */
IAV_PADDING_BOTTOM = 2, /*!< 2, bottom padding */
IAV_PADDING_LEFT = 3, /*!< 3, left padding */
IAV_PADDING_NUM = 4, /*!< 4 */
IAV_PADDING_FIRST = IAV_PADDING_TOP, /*!< IAV_PADDING_TOP */
IAV_PADDING_LAST = IAV_PADDING_NUM, /*!< IAV_PADDING_NUM */
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_blend_area {
u16 width; /*!< width of blend area */
u16 height; /*!< height of blend area */
u16 update_alpha : 1; /*!< enable / disable updating alpha table. */
u16 reserved0 : 15;
u16 alpha_pitch; /*!< buffer pitch of alpha table */
u8 padding[IAV_PADDING_NUM]; /*!< padding width/height of blend area at the borders */
u16 offset_x[IAV_BLEND_BUF_NUM]; /*!< horizontal offset of blend buffes within canvas */
u16 offset_y[IAV_BLEND_BUF_NUM]; /*!< vertical offset of blend buffer within canvas */
unsigned long alpha_addr_offset; /*!< the offset of alpha table */
};/*!< Aligned to 32 Bytes */
#define IAV_MAX_BLEND_AREA_NUM (16)
struct iav_arb_blend {
u8 blend_area_num; /*!< number of blend areas */
u8 reserved0[3];
u32 reserved1[7];
struct iav_blend_area blend_areas[IAV_MAX_BLEND_AREA_NUM] /*!< blend area configuration */;
};/*!< Aligned to 544 Bytes */
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum iav_video_proc_id {
IAV_VIDEO_PROC_DPTZ = 0x00, /*!< 0x00, This is to configure DPTZ parameters on the fly. */
IAV_VIDEO_PROC_MASK = 0x01, /*!< 0x01, This is to configure single color privacy mask on the fly. */
IAV_VIDEO_PROC_PYRAMID_ROI = 0x02, /*!< 0x02, This is to configure pyramid ROI parameters on the fly. */
IAV_VIDEO_PROC_CANVAS_FPS = 0x03, /*!< 0x03, This is to configure canvas frame rate on the fly. */
IAV_VIDEO_PROC_WARP = 0x04, /*!< 0x04, This is to configure warp cfg on the fly. */
IAV_VIDEO_PROC_VSRC_REGION = 0x05, /*!< 0x05, This is to configure vsrc region idx on the fly. Only for DOL HDR. */
IAV_VIDEO_PROC_VCAP_FLUSH = 0x06, /*!< 0x06, This is to trigger all frames flushed out from IDSP. */
IAV_VIDEO_PROC_MULTI_BLEND = 0x07, /*!< 0x07, This is to configure multi-channel blend overlap area parameters on the fly. */
IAV_VIDEO_PROC_BLEND_DPTZ = 0x08, /*!< 0x08, This is to configure multi-channel blend DPTZ parameters on the fly. */
IAV_VIDEO_PROC_VSRC_UPDATE = 0x09, /*!< 0x09, This is to update the vsrc that works on the channel. */
IAV_VIDEO_PROC_BLEND_WARP = 0x0A, /*!< 0x0A, This is to configure multi-channel blend overlap area warp parameters on the fly. */
IAV_VIDEO_PROC_MATCH_TABLE = 0x0B, /*!< 0x0B, This is to configure match table parameters for overlap areas. */
IAV_VIDEO_PROC_CANVAS_OVERLAY = 0x0C, /*!< 0x0C, This is to configure OVERLAY in canvas domain. */
IAV_VIDEO_PROC_PYRAMID_FPS = 0x0D, /*!< 0x0D, This is to configure pyramid frame rate on the fly. */
IAV_VIDEO_PROC_CANVAS_ORDER = 0x0E, /*!< 0x0E, This is to configure channel order in one canvas on the fly. */
IAV_VIDEO_PROC_ARB_BLEND = 0x0F, /*!< 0x0F, This is to configure arbitrary blend in multiple channels order. */
IAV_VIDEO_PROC_FUSION = 0x10, /*!< 0x10, This is to configure channel fusion blend area on the fly. */
IAV_VIDEO_PROC_NUM = 0x11, /*!< 0x11 */
IAV_VIDEO_PROC_FIRST = IAV_VIDEO_PROC_DPTZ, /*!< IAV_VIDEO_PROC_DPTZ */
IAV_VIDEO_PROC_LAST = IAV_VIDEO_PROC_NUM /*!< IAV_VIDEO_PROC_NUM */
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_privacy_mask {
u8 channel_id; /*!< Channel ID */
u8 enable; /*!< 0: disable, 1: enable */
u8 y; /*!< y of the mask color, only used for single color mask. */
u8 u; /*!< u of the mask color, only used for single color mask. */
u8 v; /*!< v of the mask color, only used for single color mask. */
u8 clear_user_mask : 1; /*!< Flag to clear user privacy mask memory only when PM is disabled (@ref enable = 0). 0 (default) : Keep user PM
memory as is, no clear. 1 : Clear user PM memory. */
u8 reserved0 : 7;
u16 buf_pitch; /*!< Buffer pitch. For single color mask: it is aligned to 32 bytes(in byte unit). The unit depends on the privacy mask type.
For multi color mask : it is downscaled from VIN's width. */
u16 buf_height; /*!< Buffer height. For single color mask: it is in pixel unit and equal to main buffer height.
For multi color mask : it is downscaled from VIN's height. */
u16 reserved1[3];
unsigned long data_addr_offset; /*!< Start address of privacy mask data */
};
struct iav_mask_color {
u8 V; /*!< chroma V value, used for multi color mask. */
u8 U; /*!< chroma U value, used for multi color mask. */
u8 Y; /*!< chroma Y value, used for multi color mask. */
u8 alpha; /*!< chroma alpha value, used for multi color mask. */
};
struct iav_vsrc_region {
u8 channel_id; /*!< Channel ID */
u8 map; /*!< The region index map for current channel. Only for DOL HDR. */
u8 reserved[2];
};
struct iav_vcap_flush {
u8 channel_id; /*!< Channel ID */
u8 reserved[3];
};
struct iav_video_proc {
enum iav_video_proc_id cid; /*!< Configuration item ID, @sa iav_video_proc_id */
union {
struct iav_dptz dptz;
struct iav_privacy_mask mask;
struct iav_pyramid_roi pyramid_roi;
struct iav_canvas_fps canvas_fps;
struct iav_blend_overlap blend_overlap;
struct iav_blend_dptz blend_dptz;
struct iav_vsrc_region vsrc_region;
struct iav_vcap_flush vcap_flush;
struct iav_chan_vsrc_update vsrc_update;
struct iav_blend_warp blend_warp;
struct iav_blend_match_table match_table;
struct iav_overlay_insert overlay;
struct iav_pyramid_fps pyramid_fps;
struct iav_canvas_order canvas_order;
struct iav_arb_blend arb_blend;
struct iav_fusion_cfg fusion;
} arg; /*!< Configuration items */
};
struct iav_apply_flag {
int apply;
u32 param;
};
struct iav_apply_frame_sync_flag {
int apply; /*!< apply control id. */
u32 param; /*!< apply parameters */
u32 hw_pts[IAV_MAX_CHANNEL_NUM]; /*!< hw_pts for frame sync control with IDSP. */
};
struct iav_efm_ext_pool {
u32 stream_id; /*!< EFM stream id */
u32 yuv_buf_pid; /*!< EFM YUV buffer partition id */
u32 me_buf_pid; /*!< EFM ME buffer partition id. No need when stream is MJPEG. */
u32 yuv_pitch; /*!< YUV buffer pitch. */
u32 me1_pitch; /*!< me1 buffer pitch. */
u32 me0_pitch; /*!< me0 buffer pitch. */
struct iav_window me1_size; /*!< me1 image size. */
struct iav_window me0_size; /*!< me0 image size. */
};
struct iav_efm_get_pool_info {
u32 stream_id; /*!< EFM stream id*/
u32 yuv_buf_num; /*!< EFM YUV buffer number */
u32 yuv_pitch; /*!< YUV pitch */
u32 me_buf_num; /*!< EFM ME buffer number */
u32 me1_pitch; /*!< ME1 pitch */
u32 me0_pitch; /*!< ME0 pitch */
struct iav_window yuv_size; /*!< YUV size */
struct iav_window me1_size; /*!< ME1 size */
struct iav_window me0_size; /*!< ME0 size */
u32 chroma_format; /*!< Chroma_format: 0: Mono; 1: YUV420; 2: YUV422; 3: YUV444. */
};
struct iav_efm_release_all_frame {
u8 stream_id; /*!< Release frames stream id */
u8 no_prefetch_flag; /*!< Flag for enable frame buffer pool no prefetch option */
u16 reserved;
};
struct iav_efm_request_frame {
u32 stream_id; /*!< EFM stream id*/
u16 frame_idx; /*!< EFM frame index */
u16 use_dma_buf_fd : 1; /*!< When set, dma-buf:fd will be used to describe YUV and ME data.
NOTE: YUV luma, YUV choma, ME0 and ME1 data have their own dma-buf:fd. */
u16 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u16 frame_me_idx : 4; /*!< EFM frame index for ME buffer */
u16 reserved : 10;
unsigned long yuv_luma_offset; /*!< YUV Luma data offset in IAV_PART_USR. */
unsigned long yuv_chroma_offset;/*!< YUV Chromatic data offset in IAV_PART_USR. */
unsigned long me1_offset; /*!< ME1 data offset in IAV_PART_USR. */
unsigned long me0_offset; /*!< ME0 data offset in IAV_PART_USR. */
int yuv_luma_dma_buf_fd; /* dma-buf:fd for YUV luma data */
int yuv_chroma_dma_buf_fd; /* dma-buf:fd for YUV chroma data */
int me0_dma_buf_fd; /* dma-buf:fd for ME0 data */
int me1_dma_buf_fd; /* dma-buf:fd for ME1 data */
};
struct iav_efm_handshake_frame {
u32 stream_id; /*!< EFM stream ID */
u32 frame_idx; /*!< EFM frame index */
u32 frame_pts; /*!< EFM frame PTS */
u8 is_last_frame; /*!< Flag for last_frame */
u8 use_hw_pts; /*!< HW PTS, only apply to real time's case */
u16 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u16 hold_frame : 1; /*!< The EFM frame will hold current frame after being fed to DSP. */
u16 use_stream_map : 1; /*!< Enable using stream map for multiple stream. */
u16 frame_me_idx : 4; /*!< EFM frame index for ME buffer */
u16 reserved : 9;
u32 stream_map; /*!< The bits map of mutiple encoding streams. */
u32 frame_pts_msb; /*!< EFM frame PTS in MSB u32. frame_pts_u64 = (frame_pts_msb << 32) | frame_pts */
u32 yuv_ext_offset; /*!< EFM YUV offset inside of YUV partition. Only valid when efm_ext_mem = 1. */
u32 me_ext_offset; /*!< EFM ME offset inside of ME partition. Only valid when efm_ext_mem = 1. */
};
struct iav_raw_enc_cfg {
u8 vinc_id; /*!< VIN Control ID */
u8 total_buf_num; /*!< Data total buf num */
u16 raw_max_height; /*!< RAW data max height for dram align */
u16 raw_pitch; /*!< RAW data pitch */
u16 raw_hdec_pitch; /*!< HDEC data pitch */
u16 raw_width; /*!< RAW data width */
u16 raw_hdec_width; /*!< HDEC data width */
u16 raw_height; /*!< RAW data height */
u16 raw_hdec_height; /*!< HDEC data height */
unsigned long raw_buf_addr; /*!< RAW data DRAM addr */
unsigned long raw_hdec_buf_addr; /*!< HDEC data DRAM addr */
u32 is_from_ext_mem : 1; /*!< Flag to specify whether the raw data is from external pool memory */
u32 enable_raw_low_hdec : 1; /*!< Flag to specify whether raw_low_hdec is enabled or not, 0(default): disabled. */
u32 reserved0 : 14;
u32 raw_low_hdec_height : 16; /*!< Low HDEC data height, 1/4 of raw_hdec_height, only valid
when enable_raw_low_hdec = 1 */
u16 raw_low_hdec_pitch; /*!< Low HDEC data pitch, only valid when enable_raw_low_hdec = 1 */
u16 raw_low_hdec_width; /*!< Low HDEC data width, same as raw_hdec_width, only valid when enable_raw_low_hdec = 1 */
unsigned long raw_low_hdec_buf_addr; /*!< Low HDEC data DRAM addr, only valid when enable_raw_low_hdec = 1 */
u32 reserved1[4]; /*!< Aligned to 64B */
};
struct iav_raw_enc_setup {
u8 vinc_id; /*!< VIN Control ID */
u8 raw_daddr_buf_idx; /*!< RAW data buf idx */
u8 raw_hdec_daddr_buf_idx; /*!< HDEC data buf idx */
u8 raw_low_hdec_daddr_buf_idx; /*!< Low HDEC data buf idx */
u8 reserved[4];
u64 frame_pts; /*!< Frame PTS */
u64 mono_pts; /*!< This is mono_pts, which can be used to sync with IDSP cfg for EIS. */
};
struct iav_apply_frame_sync {
u32 dsp_pts; /*!< Specify the PTS of synchronized frame to apply frame sync parameters. */
u32 stream_updated_map : 28; /*!< The stream id bit map to update sync parameters. */
u32 force_update : 1; /*!< Force to update sync parameters if the frame PTS is not found from the internal queue. */
u32 strm_sync_type : 3; /*!< Select frame sync or stream sync */
u64 stream_frame_num[IAV_STREAM_MAX_NUM_ALL]; /*!< The frame number to apply stream sync parameters. */
};
struct iav_apply_canvas_frame_sync {
u32 dsp_pts; /*!< Specify the PTS of synchronized frame to apply canvas frame sync parameters. */
u32 canvas_updated_map : 28; /*!< The canvas id bit map to update sync parameters. */
u32 force_update : 1; /*!< Force to update sync parameters if the frame PTS is not found from the internal queue. */
u32 reserved : 3;
};
struct iav_apply_idsp_enc_sync {
struct iav_apply_flag idsp_apply_flags[IAV_VIDEO_PROC_NUM];
u64 task_id[IAV_MAX_CANVAS_BUF_NUM]; /*!< Output param: the unique task id of current sync task. */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
#define IAV_CE_GO_MAP_WIDTH_ALIGN (4)
#define IAV_CE_GO_MAP_HEIGHT_ALIGN (2)
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_ce_go_map_request_buffer {
u32 chan_id : 8; /*!< Chan ID*/
u32 buffer_idx : 8; /*!< CE go map buffer index */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 reserved0 : 15;
u16 buffer_max_size; /*!< CE go map single buffer size for current channel */
u16 reserved1;
unsigned long buffer_offset; /*!< CE go map buffer offset in IAV_PART_CE_GO_MAP. */
};
struct iav_ce_go_map_handshake_buffer {
u32 chan_id : 8; /*!< Chan ID */
u32 buffer_idx : 8; /*!< Buffer index */
u32 skip_cache_sync : 1; /*!< The buffer cache will not be synced if this flag is enabled. */
u32 reserved0 : 15;
u16 buffer_pitch; /*!< Buffer pitch */
u16 buffer_width; /*!< Buffer width, It must be 1/4 of the full raw width. */
u16 buffer_height; /*!< Buffer height, It must be 1/4 of the full raw height. */
u16 reserved1;
u32 hw_pts; /*!< HW PTS for pts sync */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum iav_vcap_state {
IAV_VCAP_STATE_NORMAL = 0, /*!< 0 */
IAV_VCAP_STATE_HALT = 1, /*!< 1 */
IAV_VCAP_STATE_VSYNC_LOSS = 2, /*!< 2 */
IAV_VCAP_STATE_STATUS_ERROR = 3, /*!< 3 */
IAV_VCAP_STATE_STANDBY = 4, /*!< 4 */
IAV_VCAP_STATE_NUM = 5, /*!< 5 */
IAV_VCAP_STATE_ACTIVE = IAV_VCAP_STATE_NORMAL, /*!< 0 */
IAV_VCAP_STATE_IDLE = IAV_VCAP_STATE_HALT, /*!< 1 */
};
enum iav_vcap_cfg_id {
IAV_VCAP_CFG_STATE = 0x0000, /*!< 0x0000 */
IAV_VCAP_REPEAT_FRAME = 0x0001, /*!< 0x0001 */
IAV_VCAP_CFG_NUM, /*!< 0x0002 */
};
enum vin_idsp_apply_map {
IAV_APPLY_NONE = 0, /*!< 0 */
IAV_APPLY_VIN_CFG = (1 << 0), /*!< 1 << 0 */
IAV_APPLY_IDSP_CFG = (1 << 1), /*!< 1 << 1 */
IAV_APPLY_ALL_CFG = (IAV_APPLY_VIN_CFG | IAV_APPLY_IDSP_CFG), /*!< IAV_APPLY_VIN_CFG | IAV_APPLY_IDSP_CFG */
};
enum iav_vin_proc_id {
IAV_VIN_PROC_REPEAT = 0x00, /*!< 0x00, This is to configure VIN frame repeat parameters on the fly. */
IAV_VIN_PROC_NUM = 0x01, /*!< 0x01 */
IAV_VIN_PROC_FIRST = IAV_VIN_PROC_REPEAT, /*!< IAV_VIN_PROC_REPEAT */
IAV_VIN_PROC_LAST = IAV_VIN_PROC_NUM /*!< IAV_VIN_PROC_NUM */
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_vcap_state_cfg {
u32 vinc_map; /*!< VIN control ID map */
enum iav_vcap_state state[VIN_CONTROLLER_NUM]; /*!< vcap states */
};
struct iav_vcap_cfg {
enum iav_vcap_cfg_id cid; /*!< VCAP configuration ID */
union {
struct iav_vcap_state_cfg state_cfg;
u16 vinc_id; /*!< VIN Control ID */
} arg;
};
struct iav_vin_idsp_config {
struct vindev_wdr_gp_info vin_cfg;
struct idsp_config_s idsp_cfg;
u32 apply_map : 8; /*!< apply map @ref vin_idsp_apply_map */
u32 instant_update : 1; /*!< apply VIN or IDSP CFG to sensor or ISP instantly without timing logic */
u32 reserved : 23;
u8 resend_all_cfg_done[IMG_MAX_VIN_CHANNEL_NUM];
};
struct iav_vin_compand_config {
u8 vsrc_id; /*!< Video Source ID */
u8 comp_en; /*!< Flag to enable VIN compand option */
u8 decomp_en; /*!< Flag to enable VIN de-compand option */
u8 reserved0;
u16 comp_lut[COMP_LUT_ENTRY_NUM]; /*!< VIN compand Look-Up-Table */
u16 reserved1;
u32 decomp_lut[DECOMP_LUT_ENTRY_NUM]; /*!< VIN de-compand Look-Up-Table */
};
struct iav_vin_delay_info {
struct vindev_sht_agc_seq sht_agc[IMG_MAX_VIN_CHANNEL_NUM];
};
struct iav_vin_idsp_delay_info {
struct iav_vin_delay_info vin;
struct idsp_delay_info_s idsp;
};
struct iav_vin_repeat {
u32 frame_repeat : 1; /*!< Flag to enable VIN RAW frame repeat */
u32 reserevd : 31;
};
struct iav_vin_proc {
enum iav_vin_proc_id cid; /*!< Configuration item ID, @sa iav_vin_proc_id */
u8 vsrc_id; /*!< Video Source ID */
u8 reserved0[3];
union {
struct iav_vin_repeat vin_repeat;
} arg; /*!< Configuration items */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*! @addtogroup iav-ioctl-general-helper
* @{
*/
enum iav_nalu_type_h264 {
NT_NON_IDR = 1, /*!< 1 */
NT_IDR = 5, /*!< 5 */
NT_SEI = 6, /*!< 6 */
NT_SPS = 7, /*!< 7 */
NT_PPS = 8, /*!< 8 */
NT_AUD = 9, /*!< 9 */
};
enum iav_nalu_type_h265 {
TRAIL_N = 0, /*!< 0 */
TRAIL_R = 1, /*!< 1 */
TSA_N = 2, /*!< 2 */
TSA_R = 3, /*!< 3 */
STSA_N = 4, /*!< 4 */
STSA_R = 5, /*!< 5 */
IDR_W_RADL = 19, /*!< 19 */
IDR_N_LP = 20, /*!< 20 */
};
enum iav_debugcfg_module {
IAV_DEBUG_IAV = (1 << 0), /*!< 1 << 0 */
IAV_DEBUG_DSP = (1 << 1), /*!< 1 << 1 */
IAV_DEBUG_VIN = (1 << 2), /*!< 1 << 2 */
IAV_DEBUG_VOUT = (1 << 3), /*!< 1 << 3 */
IAV_DEBUG_AAA = (1 << 4), /*!< 1 << 4 */
};
enum iav_debugcfg_id {
IAV_DEBUGCFG_CHECK = 0x0000, /*!< 0x0000 */
IAV_DEBUGCFG_MODULE = 0x0001, /*!< 0x0001 */
IAV_DEBUGCFG_AUDIT_INT = 0x0002, /*!< 0x0002 */
IAV_DEBUGCFG_AUDIT_IOCTL = 0x0003, /*!< 0x0003 */
IAV_DEBUGCFG_CHECK_SYS_PERF = 0x0004, /*!< 0x0004 */
IAV_DEBUGCFG_AUDIT_YUV_DELAY = 0x0005, /*!< 0x0005 */
IAV_DEBUGCFG_AUDIT_IDSP = 0x0006, /*!< 0x0006 */
IAV_DEBUGCFG_AUDIT_ENC = 0x0007, /*!< 0x0007 */
IAV_DEBUGCFG_AUDIT_VOUT = 0x0008, /*!< 0x0008 */
IAV_DEBUGCFG_AUDIT_ENC_SYNC = 0x0009, /*!< 0x0009 */
IAV_DEBUGCFG_AUDIT_EIS_SYNC = 0x000A, /*!< 0x000A*/
IAV_DEBUGCFG_SKIP_IRQ = 0x000B, /*!< 0x000B*/
IAV_DEBUGCFG_AUDIT_VV_DELAY = 0x000C, /*!< 0x000C */
IAV_DEBUGCFG_AUDIT_IMAG_SCALER = 0x000D, /*!< 0x000D */
IAV_DEBUGCFG_NUM = 0x000E, /*!< 0x000E*/
IAV_DEBUGCFG_FIRST = IAV_DEBUGCFG_CHECK, /*!< IAV_DEBUGCFG_CHECK */
IAV_DEBUGCFG_LAST = IAV_DEBUGCFG_NUM, /*!< IAV_DEBUGCFG_NUM */
IAV_DEBUGCFG_CHECK_ALL = IAV_DEBUGCFG_CHECK, /*!< IAV_DEBUGCFG_CHECK */
};
enum iav_customcmd_id {
IAV_CUSTOMCMD_GENERAL_DEBUG, /*!< 0x0000 */
IAV_CUSTOMCMD_GET_EXTRA_RAW_CAP_CFG, /*!< 0x0001 */
IAV_CUSTOMCMD_SET_EXTRA_RAW_CAP_CFG, /*!< 0x0002 */
IAV_CUSTOMCMD_NUM,
IAV_CUSTOMCMD_FIRST = IAV_CUSTOMCMD_GENERAL_DEBUG, /*!< IAV_CUSTOMCMD_GENERAL_DEBUG */
IAV_CUSTOMCMD_LAST = IAV_CUSTOMCMD_NUM, /*!< IAV_CUSTOMCMD_NUM */
};
enum dsp_irq_port_type {
DSP_IRQ_PORT_GEN = 0, /*!< 0x0000 */
DSP_IRQ_PORT_VCAP, /*!< 0x0001 */
DSP_IRQ_PORT_NUM,
DSP_IRQ_PORT_FIRST = DSP_IRQ_PORT_GEN, /*!< DSP_IRQ_PORT_GEN */
DSP_IRQ_PORT_LAST = DSP_IRQ_PORT_NUM, /*!< DSP_IRQ_PORT_NUM */
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*! @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_debug_module {
u8 enable;
u8 reserved[3];
u32 flags;
u32 args[4];
};
struct iav_debug_audit {
u32 id;
u32 enable : 1;
u32 reserved0 : 31;
u64 cnt;
u64 sum;
u32 max;
u32 min;
u32 cur;
u32 reserved1;
};
struct iav_debug_idsp_audit {
u32 enable : 1; /*!< Enable/Disable idsp frame drop audit. */
u32 reserved : 31;
int idsp_frm_drop_cnt[IAV_MAX_CHANNEL_NUM]; /*!< idsp frame drop count. Each time when this audit is enabled, it will be reset to 0. */
void (*inc)(struct iav_debug_idsp_audit *idsp_audit, u8 chan_id);
};
struct iav_debug_enc_audit {
u32 enable : 1; /*!< Enable/Disable encode frame drop audit. it only audits the frame drop count due to BO check. */
u32 reserved : 31;
u32 enc_frm_drop_cnt[IAV_STREAM_MAX_NUM_ALL]; /*!< encode frame drop count. Each time when this audit is enabled, it will be reset to 0. */
void (*inc)(struct iav_debug_enc_audit *enc_audit, u8 stream_id);
};
struct iav_debug_vout_audit {
u32 enable : 1; /*!< Enable/Disable vout underflow audit. */
u32 reserved : 31;
u32 vout_uf_cnt[VOUT_NUM]; /*!< vout underflow count. Each time when this audit is enabled, it will be reset to 0. */
void (*inc)(struct iav_debug_vout_audit *vout_audit, u8 vout_id);
};
struct iav_debug_skip_dsp_irq {
u32 skip_cnt; /*!< Skip DSP ISR count. Used by internal debug purpose. */
u8 dsp_port; /*!< DSP IRQ port. */
u8 reserved[3];
};
struct iav_debug_sync_audit {
u32 enable : 1; /*!< Enable/Disable sync fail audit. */
u32 reserved : 31;
u32 sync_fail_cnt; /*!< sync fail count. Each time when this audit is enabled, it will be reset to 0. */
void (*inc)(struct iav_debug_sync_audit *sync_audit);
};
struct iav_debug_cfg {
u32 id; /*!< Not currently supported */
enum iav_debugcfg_id cid; /*!< Debug configuration item ID */
union {
u32 enable; /*!< If IAV, there is no need to check if it is enabled or not */
struct iav_debug_module module; /*!< Custom debug module configuration */
struct iav_debug_audit audit; /*!< IAV Audit debugging configuration */
struct iav_debug_idsp_audit idsp_audit; /*!< IAV IDSP frame drop audit debugging configuration */
struct iav_debug_enc_audit enc_audit; /*!< IAV encode frame drop audit debugging configuration */
struct iav_debug_vout_audit vout_audit; /*!< IAV vout underflow audit debugging configuration */
struct iav_debug_skip_dsp_irq skip_irq; /*!< DSP ISR skip debugging configuration */
struct iav_debug_sync_audit enc_sync_audit; /*!< ENC sync fail audit debugging configuration */
struct iav_debug_sync_audit eis_sync_audit; /*!< EIS sync fail audit debugging configuration */
struct iav_debug_audit vv_audit[VOUT_NUM]; /*!< VOUT-VIN delay audit debugging configuration */
} arg; /*!< IAV debug configuration */
};
struct iav_custom_gen_debug_cmd {
u32 debug_op;
u32 reserved[7];
};
struct iav_custom_extra_raw_cap_cfg {
u8 enable; /*!< Enbale/disable extra raw capture. 1:enable; 0:disable */
u8 top_lines; /*!< Specify the top lines to capture */
u8 bottom_lines; /*!< Specify the bottom lines to capture */
u8 reserved;
};
struct iav_custom_cfg {
enum iav_customcmd_id cmd_code;
union {
struct iav_custom_gen_debug_cmd debug;
struct iav_custom_extra_raw_cap_cfg extra_raw_cap[VIN_CONTROLLER_NUM];
} arg;
};
enum iav_sync_vin_frame_type {
IAV_SYNC_VIN_LF_EOF = 0, /*!< 0, end-of-frame of long frame */
IAV_SYNC_VIN_LF_SOF = 1, /*!< 1, start-of-frame of long frame */
IAV_SYNC_VIN_SF_EOF = 2, /*!< 2, end-of-frame of short frame */
IAV_SYNC_VIN_SF_SOF = 3, /*!< 3, start-of-frame of short frame */
IAV_SYNC_VIN_FRAME_NUM = 4,
IAV_SYNC_VIN_FRAME_FIRST = IAV_SYNC_VIN_LF_EOF,
IAV_SYNC_VIN_FRAME_LAST = IAV_SYNC_VIN_FRAME_NUM,
};
struct iav_sync_vin_frame {
u32 chan_wait_map; /*!< This is a bit map to specify channel map to synchronize. */
enum iav_sync_vin_frame_type sync_type[IAV_MAX_CHANNEL_NUM]; /*!< Specify the type to synchronize with the VIN frame. The default value is 0. */
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*!
* @addtogroup iav-ioctl-dec-helper
* @{
*/
#define IAV_MAX_DECODER_NUMBER 16
enum iav_decoder_type {
IAV_DEC_TYPE_H264 = 0, /*!< 0 */
IAV_DEC_TYPE_H265 = 1, /*!< 1 */
IAV_DEC_TYPE_JPEG = 2, /*!< 2 */
IAV_DEC_TYPE_NUM = 3, /*!< 3 */
};
enum iav_decode_op {
IAV_DEC_PAUSE = 0, /*!< 0 */
IAV_DEC_RESUME = 1, /*!< 1 */
IAV_DEC_STEP = 2, /*!< 2 */
};
enum iav_decode_direction {
IAV_DEC_DIR_FW = 0, /*!< 0 */
IAV_DEC_DIR_BW = 1, /*!< 1 */
};
enum iav_decode_scan_mode {
IAV_DEC_SCAN_MODE_ALL_FRAMES = 0, /*!< 0 */
IAV_DEC_SCAN_MODE_I_ONLY = 1, /*!< 1 */
};
/*! @} */ /* End of iav-ioctl-dec-helper */
/*! @addtogroup iav-ioctl-dec-struct
* @{
*/
struct iav_decode_mode_config {
u8 num_decoder; /*!< Number of decoder. */
u8 num_vout; /*!< Number of VOUT */
u8 support_ff_fb_bw :2; /*!< Playback will support fast FW/BW. Please note that this can need more DRAM usage in DSP if enabled. */
u8 support_all_frame_backward :2; /*!< Output: Support all frames backward or not. */
u8 not_reset_vout : 2; /*!< Not reset VOUT, when vout setting does not change */
u8 reserved0 : 2;
u8 reserved1;
u8 decoder_type[IAV_MAX_DECODER_NUMBER]; /*!< Decoder type */
u32 max_width; /*!< Deprecated. Maximum video width for each decoder */
u32 max_height; /*!< Deprecated. Maximum video height for each decoder */
u32 max_vout0_width; /*!< Deprecated. Maximum video width for vout0 */
u32 max_vout0_height; /*!< Deprecated. Maximum video height vout0 */
u32 max_vout1_width; /*!< Deprecated. Maximum video width for vout1 */
u32 max_vout1_height; /*!< Deprecated. Maximum video height for vout1 */
u8 enable_vout[IAV_MAX_DECODER_NUMBER]; /*!< Deprecated. Vout enable flag */
};
struct iav_decoder_info {
u8 decoder_id; /*!< Decoder instance ID */
u8 decoder_type; /*!< Decoder type, @sa iav_decoder_type */
u8 num_vout; /*!< Number of VOUT */
u8 setup_done; /*!< Ignore it */
u32 video_width; /*!< Video width */
u32 video_height; /*!< Video height */
u32 bsb_size; /*!< Size of bitstream-buffer */
unsigned long bsb_start_offset; /*!< Start offset of bitstream-buffer */
};
struct iav_decode_video {
u8 decoder_id; /*!< Decoder ID */
u8 num_frames; /*!< Not in use. Number of frames in bitstream */
u8 reserved[2];
u32 first_frame_display; /*!< Specify the PTS of first frame that will be displayed. */
unsigned long start_ptr_offset; /*!< Video data's start offset in bitstream buffer */
unsigned long end_ptr_offset; /*!< Video data's end offset in bitstream buffer */
};
struct iav_decode_jpeg {
u8 decoder_id; /*!< Decoder ID */
u8 reserved[3];
u32 size; /*!< Size of JPEG data */
unsigned long start_offset; /*!< JPEG data start offset in bitstream buffer */
};
struct iav_decode_bsb {
u8 decoder_id; /*!< Decoder ID */
u8 reserved[3];
unsigned long start_offset; /*!< Request free zoom's start offset */
u32 room; /*!< Request free zoom's size, minus 256 byte for avoid read_offset == write_offset*/
//read only
u32 free_room; /*!< DSP's free zoom (read only) */
unsigned long dsp_read_offset; /*!< DSP's read offset (read only) */
};
struct iav_decode_stop {
u8 decoder_id; /*!< Decoder ID */
u8 stop_flag; /*!< Stop flag: 0: End the playback, 1: Keep showing last frame,
will continue playback when feeding new data */
u8 reserved[6];
};
struct iav_decode_trick_play {
u8 decoder_id; /*!< Decoder ID */
u8 trick_play; /*!< Trick play type, see IAV_TRICK_PLAY */
u8 reserved[6];
};
struct iav_decode_speed {
u8 decoder_id; /*!< Decoder ID */
u8 reserved[3];
u8 direction; /*!< See @ref iav_decode_direction, 0: forward, 1: backward*/
u8 scan_mode; /*!< See @ref iav_decode_scan_mode */
u16 speed; /*!< Playback speed, 8.8 fix point format */
};
struct iav_decode_wait_eos {
u8 decoder_id; /*!< Decoder ID */
u8 timeout_ticks; /*!< time out ticks, 0: No timeout */
u8 reserved[6];
};
struct iav_decode_status {
u8 decoder_id; /*!< Decoder ID */
u8 is_started : 1; /*!< Decoder is started */
u8 is_send_stop_cmd : 1; /*!< Decoder has been sent stop command */
u8 non_block_flag : 1; /*!< Flag to specify query decode status in non blocking way */
u8 reserved0 : 5;
u8 reserved[6];
u32 last_pts; /*!< Last showing frame's pts */
u32 decode_state; /*!< DSP decode status */
u32 error_status; /*!< DSP decode error status */
u32 total_error_count; /*!< Total DSP met errors */
u32 decoded_pic_number; /*!< Total decoded picture number */
//bit stream buffer
u32 room; /*!< Free zoom left in bitstream buffer,
minus 256 byte for avoid read_offset == write_offset */
unsigned long write_offset; /*!< ARM write offset, in bitstream buffer */
unsigned long dsp_read_offset; /*!< DSP read offset, in bitstream buffer */
u32 free_room; /*!< DSP reported free zoom */
//debug
u32 irq_count; /*!< IRQ count. Debug only. */
unsigned long yuv422_y_addr; /*!< Luma address of display frame */
unsigned long yuv422_uv_addr; /*!< Chroma address of display frame */
u32 pic_num; /*!< decoded frames number */
u32 pts_low; /*!< dsp pts lower 32 bits part */
u32 pts_high; /*!< dsp pts higer 32 bits part */
struct iav_yuv_cap decoded_pic_info; /*!< decoded frame information */
struct iav_yuv_cap decoded_still_pic_info; /*!< decoded still picture information */
};
/*! @} */ /* End of iav-ioctl-dec-struct */
/*!
* @addtogroup iav-ioctl-general-helper
* @{
*/
/*! @def IAV_DSP_CMD_SIZE
* @brief define the cmd size of DSP cmd
*/
#define IAV_DSP_CMD_SIZE (256) // 256 Byte
#define IAV_MAX_BATCH_NUM (24)
#define IAV_MAX_CFG_NUM (16)
#define IAV_MAX_PREFIX_BUF_SIZE (128) // 128 Byte
#define IAV_MIN_PARSED_BUF_SIZE (4096) // 4 KB
#define IAV_MAX_PARSED_BUF_SIZE (8192) // 8 KB
enum iav_dsp_dump_cmd_ctrl_type {
IAV_DSP_DUMP_CMD_CTRL_TYPE_DO_DUMP = 0, /*!< Enable/Disable DSP cmd dump */
IAV_DSP_DUMP_CMD_CTRL_TYPE_INFORM_PID = 1, /*!< Configurate the memory partition to store the dumped DSP cmd */
IAV_DSP_DUMP_CMD_CTRL_TYPE_PARSE_CMD = 2, /*!< Parse DSP cmd */
};
enum iav_dsp_batch_cmd_type {
DSP_BATCH_CMD_TYPE_ENC = 0, /*!< 0 */
DSP_BATCH_CMD_TYPE_POSTP = 1, /*!< 1 */
DSP_BATCH_CMD_TYPE_VOUT0 = 2, /*!< 2 */
DSP_BATCH_CMD_TYPE_VOUT1 = 3, /*!< 3 */
DSP_BATCH_CMD_TYPE_PREP = 4, /*!< 4 */
DSP_BATCH_CMD_TYPE_NUM = 5, /*!< 5 */
DSP_BATCH_CMD_TYPE_FIRST = DSP_BATCH_CMD_TYPE_ENC, /*!< DSP_BATCH_CMD_TYPE_ENC */
DSP_BATCH_CMD_TYPE_LAST = DSP_BATCH_CMD_TYPE_NUM, /*!< DSP_BATCH_CMD_TYPE_NUM */
};
enum iav_dsp_cfg_type {
DSP_CFG_TYPE_ENC = 0, /*!< 0 */
DSP_CFG_TYPE_CANVAS = 1, /*!< 1 */
DSP_CFG_TYPE_DISPLAY = 2, /*!< 2 */
DSP_CFG_TYPE_VIN_FLOW = 3, /*!< 3 */
DSP_CFG_TYPE_VIN_DBUF = 4, /*!< 4 */
DSP_CFG_TYPE_VIN = 5, /*!< 5 */
DSP_CFG_TYPE_CHAN = 6, /*!< 6 */
DSP_CFG_TYPE_WARP = 7, /*!< 7 */
DSP_CFG_TYPE_NUM = 8, /*!< 8 */
DSP_CFG_TYPE_FIRST = DSP_CFG_TYPE_ENC, /*!< DSP_CFG_TYPE_ENC */
DSP_CFG_TYPE_LAST = DSP_CFG_TYPE_NUM, /*!< DSP_CFG_TYPE_NUM */
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*!
* @addtogroup iav-ioctl-general-struct
* @{
*/
struct iav_dsp_dump_cmd_ctrl_parse {
u8 dsp_cmd[IAV_DSP_CMD_SIZE]; /*!< IN: the dsp cmd to be parsed */
char *prefix_buf; /*!< IN: the prefix buffer to be inserted into parsed_result.
This buffer is allocated by user application. */
u32 prefix_buf_size; /*!< IN: prefix buffer size */
u32 result_buf_size; /*!< IN: the parsed result buffer size */
u8 has_cfg_addr : 1; /*!< OUT: flag to show whether the cmd has cfg addr */
u8 is_batch_cmd : 1; /*!< OUT: flag to show whether current dsp cmd is a batch cmd */
u8 reserved0 : 6;
u8 cfg_num; /*!< OUT: the number of cfg buffers */
u8 reserved1[2];
u32 reserved2;
char *result_buf; /*!< IN OUT: the buffer to store the parsed result.
This buffer is allocated by user application. Suggested to be >= 4KB. */
u32 batch_cmd_addr[IAV_MAX_BATCH_NUM]; /*!< OUT: physical start address of batch cmds */
u8 batch_cmd_type[IAV_MAX_BATCH_NUM]; /*!< OUT: batch cmd type @ref iav_dsp_batch_cmd_type */
u8 batch_cmd_num[IAV_MAX_BATCH_NUM]; /*!< OUT: cmd number of each batch */
u8 chan_batch_cmd_num[IAV_MAX_CHANNEL_NUM]; /*!< OUT: channel batch cmd number,
only valid when DSP_BATCH_CMD_TYPE_PREP is available */
u32 chan_batch_cmd_addr[IAV_MAX_CHANNEL_NUM]; /*!< OUT: channel batch cmd addr,
only valid when DSP_BATCH_CMD_TYPE_PREP is available */
u32 cfg_type[IAV_MAX_CFG_NUM]; /*!< OUT: cfg buffer type */
u32 cfg_buf_addr[IAV_MAX_CFG_NUM]; /*!< OUT: physical start address of cfg buffer */
u32 cfg_buf_size[IAV_MAX_CFG_NUM]; /*!< OUT: buffer size of cfg buffer */
};
struct iav_dsp_dump_cmd_ctrl {
u32 ctrl_type; /*!< Control type, @sa iav_dsp_dump_cmd_ctrl_type */
union {
struct iav_dsp_dump_cmd_ctrl_parse parse;
};
};
/*! @} */ /* End of iav-ioctl-general-struct */
/*!
* @addtogroup iav-ioctl-general-helper
* @{
*/
/*! @def IAVENCIOC_MAGIC
* @brief IAVENCIOC_MAGIC.
*/
#define IAVENCIOC_MAGIC 'V'
/*! @def IAVENC_IO(nr)
* @brief ioctl none of (nr).
*/
#define IAVENC_IO(nr) _IO(IAVENCIOC_MAGIC, nr)
/*! @def IAVENC_IOR(nr)
* @brief ioctl read of (nr).
*/
#define IAVENC_IOR(nr, size) _IOR(IAVENCIOC_MAGIC, nr, size)
/*! @def IAVENC_IOW(nr)
* @brief ioctl write of (nr).
*/
#define IAVENC_IOW(nr, size) _IOW(IAVENCIOC_MAGIC, nr, size)
/*! @def IAVENC_IOWR(nr)
* @brief ioctl read write of (nr).
*/
#define IAVENC_IOWR(nr, size) _IOWR(IAVENCIOC_MAGIC, nr, size)
/*! @enum IAV_ENC_IOC
* @brief IAV_ENC_IOC Enumerations
*/
enum IAV_ENC_IOC {
IOC_STATE = 0x00, /*!< 0x00, For DSP & Driver (0x00 ~ 0x0F) */
IOC_CHIP_ID = 0x01, /*!< 0x01 */
IOC_DSP_LOG = 0x02, /*!< 0x02 */
IOC_DSP_INFO = 0x03, /*!< 0x03 */
IOC_DSP_VP_CFG = 0x04, /*!< 0x04 */
IOC_QUERY_INFO = 0x05, /*!< 0x05 */
IOC_QUERY_ENC_MODE_CAP = 0x06, /*!< 0x06 */
IOC_QUERY_ENC_BUF_CAP = 0x07, /*!< 0x07 */
IOC_DSP_BOOT_CFG = 0x08, /*!< 0x08 */
IOC_ENTER_IDLE = 0x10, /*!< 0x10, For system (0x10 ~ 0x3F) */
IOC_ENABLE_PREVIEW = 0x11, /*!< 0x11 */
IOC_START_ENCODE = 0x12, /*!< 0x12 */
IOC_STOP_ENCODE = 0x13, /*!< 0x13 */
IOC_ABORT_ENCODE = 0x14, /*!< 0x14 */
IOC_SYSTEM_RESOURCE = 0x15, /*!< 0x15 */
IOC_CHAN_CFG = 0x16, /*!< 0x16 */
IOC_CANVAS_CFG = 0x17, /*!< 0x17 */
IOC_PYRAMID_CFG = 0x18, /*!< 0x18 */
IOC_STREAM_RESOURCE = 0x19, /*!< 0x19 */
IOC_GDMA_COPY = 0x1A, /*!< 0x1A */
IOC_QUERY_DESC = 0x1B, /*!< 0x1B */
IOC_QUERY_MEMBLOCK = 0x1C, /*!< 0x1C */
IOC_EFM_PROC = 0x1D, /*!< 0x1D */
IOC_RAW_ENC = 0x1E, /*!< 0x1E */
IOC_MEM_PART = 0x1F, /*!< 0x1F */
IOC_PYRAMID_BUF = 0x20, /*!< 0x20 */
IOC_SYNC_CACHE_MEM_PART = 0x21, /*!< 0x21 */
IOC_CANVAS_BUF = 0x22, /*!< 0x22 */
IOC_RESET = 0x23, /*!< 0x23 */
IOC_MEM_LAYOUT = 0x24, /*!< 0x24 */
IOC_ANON_MEM_PART = 0x25, /*!< 0x25 */
IOC_POLL_EVENT_CFG = 0x26, /*!< 0x26 */
IOC_RAW_BUF = 0x27, /*!< 0x27 */
IOC_SET_VOUT_MAX_RES_CFG= 0x28, /*!< 0x28 */
IOC_CE_GO_MAP_PROC = 0x29, /*!< 0x29 */
IOC_STREAM_CFG = 0x40, /*!< 0x40, For encode control (0x40 ~ 0x5F) */
IOC_H264_CFG = 0x41, /*!< 0x41 */
IOC_H265_CFG = 0x42, /*!< 0x42 */
IOC_MJPEG_CFG = 0x43, /*!< 0x43 */
IOC_FRAME_SYNC = 0x44, /*!< 0x44 */
IOC_OVERLAY_INSERT = 0x45, /*!< 0x45 */
IOC_FPS_SUGGEST = 0x46, /*!< 0x46 */
IOC_FRAMEDESC_CTRL = 0x47, /*!< 0x47 */
IOC_BLUR_INSERT = 0x48, /*!< 0x48 */
IOC_YUV_REMAP_INSERT = 0x49, /*!< 0x49 */
IOC_CANVAS_FRAME_SYNC = 0x4A, /*!< 0x4A */
IOC_VCAP_CFG = 0x60, /*!< 0x60, For VIN & IDSP & VCAP control (0x60 ~ 0x6F) */
IOC_WARP_CTRL = 0x61, /*!< 0x61 */
IOC_VIDEO_PROC = 0x62, /*!< 0x62 */
IOC_VIN_IDSP = 0x63, /*!< 0x63 */
IOC_WAIT_IDSP_FRAME = 0x64, /*!< 0x64 */
IOC_VIN_COMP = 0x65, /*!< 0x65 */
IOC_IMG_SCALE = 0x66, /*!< 0x66 */
IOC_WAIT_SKIP_IDSP_CFG = 0x67, /*!< 0x67 */
IOC_VIN_PROC = 0x68, /*!< 0x68 */
IOC_SYNC_VIN_FRAME = 0x69, /*!< 0x69 */
IOC_AISP_CFG = 0x70, /*!< 0x70, For AISP (Ambarella / Custom AISP) control (0x70 ~ 0x7F) */
IOC_ISP_NN_GFG = 0x71, /*!< 0x71 */
IOC_MULTI_REGION_DPTZ_CTRL = 0x72, /*!< 0x72 */
IOC_IDSP_SYNC_CTRL = 0x73, /*!< 0x73 */
IOC_TEST = 0xD0, /*!< 0xD0, For Misc setting (0xD0 ~ 0xEF) */
IOC_DEBUG = 0xD1, /*!< 0xD1 */
IOC_AUDIT = 0xD2, /*!< 0xD2 */
IOC_DRAM_TEST = 0xD3, /*!< 0xD3 */
IOC_DSP_HEALTH = 0xD4, /*!< 0xD4 */
IOC_CUSTOM = 0xF0, /*!< 0xF0, Reserved (0xF0 ~ 0xFF) */
};
/*! @} */ /* End of iav-ioctl-general-helper */
/*!
* @addtogroup iav-ioc-enc-use-drv
* @{
*/
/*!
* This API can be invoked during any state to return the current device driver state.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_GET_IAV_STATE IAVENC_IOR(IOC_STATE, u32)
/*!
* This API can be invoked during any state to retrieve chip ID information after the DSP is booted.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_GET_CHIP_ID IAVENC_IOR(IOC_CHIP_ID, u32)
/*!
* This API sets the DSP log level for the debug.
* This API is suggested to be invoked by single user.
*/
#define IAV_IOC_SET_DSP_LOG IAVENC_IOW(IOC_DSP_LOG, struct iav_dsplog_setup *)
/*!
* This API can be used to return the current device driver state.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_DRV_DSP_INFO IAVENC_IOWR(IOC_DSP_INFO, struct iav_driver_dsp_info *)
/*
* This API can be invoked during any state to set the IAV audit configuration.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_SET_AUDIT_CONFIG IAVENC_IOW(IOC_AUDIT, struct iav_audit_cfg *)
/*
* This API can be invoked during any state to fetch the IAV audit configuration.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_GET_AUDIT_CONFIG IAVENC_IOR(IOC_AUDIT, struct iav_audit_cfg *)
/*!
* This API can be invoked during any state to query IAV information such as the boot mode, driver version,
* canvas, stream, privacy mask, and BSB status information.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_QUERY_INFO IAVENC_IOWR(IOC_QUERY_INFO, struct iav_queryinfo *)
/*
* This API can be invoked during any state to set the DSP health guard configuration.
*/
#define IAV_IOC_SET_DSP_HEALTH_CONFIG IAVENC_IOW(IOC_DSP_HEALTH, struct iav_dsp_health_cfg *)
/*
* This API can be invoked during any state to get the DSP health guard configuration.
*/
#define IAV_IOC_GET_DSP_HEALTH_CONFIG IAVENC_IOR(IOC_DSP_HEALTH, struct iav_dsp_health_cfg *)
/*! @} */ /* End of iav-ioc-enc-use-drv */
/*!
* @addtogroup iav-ioc-enc-use-raw
* @{
*/
/*!
* This API can be used during the preview or encoding states to feed raw
* buffers in the channel raw manual-feed mode.
* This API can only be invoked by single user.
*/
#define IAV_IOC_FEED_RAW_BUF IAVENC_IOW(IOC_RAW_BUF, struct iav_feed_raw *)
/*!
* This API can be used during any state to release the raw buffer locked
* by IAV_IOC_QUERY_DESC (IAV_DESC_RAW) in the channel raw manual-feed mode.
* This API can only be invoked by single user.
*/
#define IAV_IOC_RELEASE_RAW_BUF IAVENC_IOWR(IOC_RAW_BUF, struct iav_feed_raw *)
/*! @} */ /* End of iav-ioc-enc-use-raw */
/*!
* @addtogroup iav-ioc-enc-use-pyra
* @{
*/
/*!
* This API can be used during the preview or encoding states to feed pyramid
* buffers in the pyramid manual-feed mode.
* This API can only be invoked by single user.
*/
#define IAV_IOC_FEED_PYRAMID_BUF IAVENC_IOW(IOC_PYRAMID_BUF, struct iav_feed_pyramid *)
/*!
* This API can be used during any state to release the pyramid buffer locked
* by IAV_IOC_QUERY_DESC (IAV_DESC_PYRAMID) in the pyramid manual-feed mode.
* This API can only be invoked by single user.
*/
#define IAV_IOC_RELEASE_PYRAMID_BUF IAVENC_IOWR(IOC_PYRAMID_BUF, struct iav_pyramiddesc *)
/*! @} */ /* End of iav-ioc-enc-use-pyra */
/*!
* @addtogroup iav-ioc-enc-use-canvas
* @{
*/
/*!
* This API can be used during the preview or encoding states to feed canvas
* buffers in the canvas manual-feed mode.
* There are some restrictions for canvas manual-feed mode:
* 1. Either in single channel or multi-channel cases, canvas must be from single
* source buffer output. It cannot be composited by multiple source buffers output.
* 2. For now, the manual feed can only support one canvas, it can be either main
* buffer or anyone of the sub source buffers. Future SDK update might support
* multiple canvas work in manual feed mode simultaneously.
* This API can only be invoked by single user.
*/
#define IAV_IOC_FEED_CANVAS_BUF IAVENC_IOW(IOC_CANVAS_BUF, struct iav_feed_canvas *)
/*!
* This API can be used during any state to release the canvas buffer locked
* by IAV_IOC_QUERY_DESC (IAV_DESC_CANVAS) in the canvas manual-feed mode.
* This API can only be invoked by single user.
*/
#define IAV_IOC_RELEASE_CANVAS_BUF IAVENC_IOWR(IOC_CANVAS_BUF, struct iav_canvasdesc *)
/*!
* This API can be invoked during ANY state to get canvas frame sync related parameters.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_GET_CANVAS_FRAME_SYNC_PROC IAVENC_IOWR(IOC_CANVAS_FRAME_SYNC, struct iav_canvas_sync_cfg *)
/*!
* This API can be invoked during ANY state to configure canvas frame sync related parameters.
* This API is mainly used for application to prepare the canvas configure parameters
* in frame accurate level. This API works with @ref IAV_IOC_GET_CANVAS_FRAME_SYNC_PROC
* This API can be invoked by multiple users simultaneously.
* and @ref IAV_IOC_APPLY_CANVAS_FRAME_SYNC_PROC.
*/
#define IAV_IOC_CFG_CANVAS_FRAME_SYNC_PROC IAVENC_IOW(IOC_CANVAS_FRAME_SYNC, struct iav_canvas_sync_cfg *)
/*!
* This API can be invoked during PREVIEW/ENCODING state to configure frame sync related
* parameters. This API works with @ref IAV_IOC_GET_CANVAS_FRAME_SYNC_PROC
* This API can be invoked by multiple users simultaneously.
* and @ref IAV_IOC_CFG_CANVAS_FRAME_SYNC_PROC.
*/
#define IAV_IOC_APPLY_CANVAS_FRAME_SYNC_PROC IAVENC_IOW(IOC_CANVAS_FRAME_SYNC, u8)
/*! @} */ /* End of iav-ioc-enc-use-canvas */
/*!
* @addtogroup iav-ioc-enc-use-sys
* @{
*/
/*!
* This API can be invoked to reset IAV and DSP and if successful, it brings IAV and DSP
* to the INIT state.
* This API can only be invoked by single user.
*/
#define IAV_IOC_RESET IAVENC_IOW(IOC_RESET, u8)
/*!
* This API can be invoked during init state to configure DSP boot params.
* This API is suggested to be invoked by single user.
*/
#define IAV_IOC_SET_DSP_BOOT_CFG IAVENC_IOW(IOC_DSP_BOOT_CFG, struct iav_dsp_boot_params *)
/*!
* This API can be invoked during idle state to set AISP (including Ambarella / Custom AISP) params.
* This API is suggested to be invoked by single user.
*/
#define IAV_IOC_SET_AISP_CFG IAVENC_IOW(IOC_AISP_CFG, struct iav_aisp_params *)
/*!
* This API can be invoked during any state to get AISP (including Ambarella / Custom AISPs) params.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_GET_AISP_CFG IAVENC_IOR(IOC_AISP_CFG, struct iav_aisp_params *)
/*!
* This API can be invoked during idle state to set NN params.
* This API is suggested to be invoked by single user.
*/
#define IAV_IOC_SET_ISP_NN_CFG IAVENC_IOW(IOC_ISP_NN_GFG, struct iav_isp_nn_params *)
/*!
* This API can be invoked during any state to get NN params.
* This API can be invoked by multiple users simultaneously.
*/
#define IAV_IOC_GET_ISP_NN_CFG IAVENC_IOR(IOC_ISP_NN_GFG, struct iav_isp_nn_params *)
/*!
* This API can be invoked to configure VOUT maximum resource during DSP INIT state.
* This API is suggested to be invoked by single user.
*/
#define IAV_IOC_SET_VOUT_MAX_RES_CFG IAVENC_IOW(IOC_SET_VOUT_MAX_RES_CFG, struct vout_max_res_params *)
/*!
* This API can be invoked to disable preview and if successful, it brings the
* driver to enter the IDLE state.
* This API is suggested to be invoked by single user.
*/
#define IAV_IOC_ENTER_IDLE IAVENC_IOW(IOC_ENTER_IDLE, u8)
/*!
* This API can be invoked to enable preview and encoding can be started only
* in the preview state.
* This API is suggested to be invoked by single user.
*/
#define IAV_IOC_ENABLE_PREVIEW IAVENC_IOW(IOC_ENABLE_PREVIEW, u8)
/*!
* This API can be invoked in init state to test DSP DRAM eff
iav_ioctl.h解释
最新推荐文章于 2025-12-15 12:46:33 发布
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