【System Verilog and UVM基础入门19】UVM_DISABLE_AUTO_ITEM_RECORDING用法说明

目录

UVM介绍

UVM_DISABLE_AUTO_ITEM_RECORDING用法说明

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UVM介绍

UVM stands for Universal Verfication Methodology. t is a standardized methodology for verifying digital designs and systems-on-chip (SoCs) in the semiconductor industry. UVM is built on top of the SystemVerilog language and provides a frameworkfor creating modular, reusable testbench components that can be easily integrated into the design verification process. lt alsoincludes a set of guidelines and best practices for developing testbenches, as well as a methodology for running simulationsand analyzing results.
UVM has become the de facto standard for design verification in the semiconductor industry, and is widely used by chipdesigners and verification engineers to verify the correctness and functionality of their designs.
 

UVM_DISABLE_AUTO_ITEM_RECORDING用法说明

在我们的验证环境中，往往会用到UVM_DISABLE_AUTO_ITEM_RECORDING这个宏，删掉它确实可以规避问题，但是不能真正的解决问题。

原文链接：https://blog.youkuaiyun.com/weixin_39662684/article/details/109361626

 调试ral模型时，调用write函数对寄存器进行写操作，发现操作没有完成.driver中在get_next_item之后也调用了item_done.开始以为是ral模型中参数配置错误导致的，分析完代码之后没有发现问题.
通过添加打印信息逐步定位发现是因为makefile中添加了UVM_DISABLE_AUTO_ITEM_RECORDING导致的.(后续会进一步分析)
1.reg2bus
寄存器访问时首先会将uvm_reg_bus_op转换为自定义的xaction形式，之后通过调用start_item和finish_item完成xaction的发送.发送完成之后，通过bus_req.end_event.wait_on()等待交互结束.

2.bus_req
bus_req的类型是uvm_sequence_item,uvm_sequence_item继承于uvm_transaction，定义了end_event.它等待对应的xaction结束之后才会往下运行.在finish_item中调用了UVM_DISABLE_AUTO_ITEM_RECORDING，代码如下：

定义此宏之后，便不会调用sequencer.end_tr(item）从而导致等待不到end_event，进而导致寄存器访问失败.
3.调用end_tr
在定义此宏之后，driver中调用item_done后，需要调用end_tr出发end_event.

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