systemverilog语法高亮设置

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已于 2022-09-19 23:26:48 修改 · 2.5k 阅读

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#vim #编辑器

于 2022-09-19 23:20:12 首次发布

1：打开家目录下的.vimrc文件配置： gvim .vimrc

syntax on
filetype on
filetype plugin on
filetype indent on

2:在家目录下新建.vim文件夹

mkdir .vim

3:进入.vim文件夹 ,并建立ftdetect、syntax文件夹

mkdir ftdetect syntax

4：进入ftdetect文件夹，并新建sv.vim文件

au BufRead,BufNewFile *.sv set filetype=verilog_systemverilog

5:将systemverilog的高亮检测文件（verilog_systemverilog.vim）放置到syntax目录下

6：在终端输入

source .vimrc

note：filetype=verilog_systemverilog 与高亮检测文件verilog_systemverilog.vim 名称需一致

verilog_systemverilog.vim如下：

"-------------------------------------------------------------------------------------
" Vim syntax file
" Language:     Verilog/SystemVerilog HDL + UVM
"-------------------------------------------------------------------------------------

if version < 600
   syntax clear
elseif exists("b:current_syntax")
   finish
endif


" Read in Verilog syntax files
if version < 600
   so syntax/verilog.vim
else
   runtime! syntax/verilog.vim
endif


syn sync lines=1000

"##########################################################
"       SystemVerilog Syntax
"##########################################################

syn keyword verilogStatement   module endmodule
syn keyword verilogStatement   always_comb always_ff always_latch
syn keyword verilogStatement   class endclass
syn keyword verilogStatement   virtual local const protected
syn keyword verilogStatement   package endpackage
syn keyword verilogStatement   rand randc constraint randomize
syn keyword verilogStatement   with inside dist
syn keyword verilogStatement   randcase
syn keyword verilogStatement   sequence endsequence randsequence 
syn keyword verilogStatement   get_randstate set_randstate
syn keyword verilogStatement   srandom
syn keyword verilogStatement   logic bit byte time
syn keyword verilogStatement   int longint shortint
syn keyword verilogStatement   struct packed
syn keyword verilogStatement   final
syn keyword verilogStatement   import export
syn keyword verilogStatement   context pure
syn keyword verilogStatement   void shortreal chandle string
syn keyword verilogStatement   clocking endclocking
syn keyword verilogStatement   interface endinterface modport
syn keyword verilogStatement   cover covergroup coverpoint endgroup
syn keyword verilogStatement   property endproperty
syn keyword verilogStatement   program endprogram
syn keyword verilogStatement   bins binsof illegal_bins ignore_bins
syn keyword verilogStatement   alias matches solve static assert
syn keyword verilogStatement   assume super before expect bind
syn keyword verilogStatement   extends null tagged extern this
syn keyword verilogStatement   first_match throughout timeprecision
syn keyword verilogStatement   timeunit priority type union unique
syn keyword verilogStatement   uwire var cross ref wait_order intersect
syn keyword verilogStatement   wildcard within
syn keyword verilogStatement   semaphore triggered
syn keyword verilogStatement   std
syn keyword verilogStatement   new

syn keyword verilogTypeDef     typedef enum

syn keyword verilogConditional iff

syn keyword verilogRepeat      return break continue
syn keyword verilogRepeat      do while foreach

syn keyword verilogLabel       join_any join_none forkjoin

syn match   verilogGlobal      "`begin_\w\+"
syn match   verilogGlobal      "`end_\w\+"
syn match   verilogGlobal      "`remove_\w\+"
syn match   verilogGlobal      "`restore_\w\+"

syn match   verilogGlobal      "`[a-zA-Z0-9_]\+\>"

syn match   verilogNumber      "\<[0-9][0-9_\.]\=\([fpnum]\|\)s\>"
syn match   verilogNumber      "\<[0-9][0-9_\.]\=step\>"

syn match   verilogMethod      "\.atobin\>"
syn match   verilogMethod      "\.atohex\>"
syn match   verilogMethod      "\.atoi\>"
syn match   verilogMethod      "\.atooct\>"
syn match   verilogMethod      "\.atoreal\>"
syn match   verilogMethod      "\.await\>"
syn match   verilogMethod      "\.back\>"
syn match   verilogMethod      "\.bintoa\>"
syn match   verilogMethod      "\.clear\>"
syn match   verilogMethod      "\.compare\>"
syn match   verilogMethod      "\.data\>"
syn match   verilogMethod      "\.delete\>"
syn match   verilogMethod      "\.empty\>"
syn match   verilogMethod      "\.eq\>"
syn match   verilogMethod      "\.erase\>"
syn match   verilogMethod      "\.erase_range\>"
syn match   verilogMethod      "\.exists\>"
syn match   verilogMethod      "\.find\>"
syn match   verilogMethod      "\.find_first\>"
syn match   verilogMethod      "\.find_first_index\>"
syn match   verilogMethod      "\.find_index\>"
syn match   verilogMethod      "\.find_last\>"
syn match   verilogMethod      "\.find_last_index\>"
syn match   verilogMethod      "\.finish\>"
syn match   verilogMethod      "\.first\>"
syn match   verilogMethod      "\.front\>"
syn match   verilogMethod      "\.get\>"
syn match   verilogMethod      "\.getc\>"
syn match   verilogMethod      "\.hextoa\>"
syn match   verilogMethod      "\.icompare\>"
syn match   verilogMethod      "\.index\>"
syn match   verilogMethod      "\.insert\>"
syn match   verilogMethod      "\.insert_range\>"
syn match   verilogMethod      "\.itoa\>"
syn match   verilogMethod      "\.kill\>"
syn match   verilogMethod      "\.last\>"
syn match   verilogMethod      "\.len\>"
syn match   verilogMethod      "\.max\>"
syn match   verilogMethod      "\.min\>"
syn match   verilogMethod      "\.name\>"
syn match   verilogMethod      "\.neq\>"
syn match   verilogMethod      "\.new\>"
syn match   verilogMethod      "\.next\>"
syn match   verilogMethod      "\.num\>"
syn match   verilogMethod      "\.octtoa\>"
syn match   verilogMethod      "\.peek\>"
syn match   verilogMethod      "\.pop_back\>"
syn match   verilogMethod      "\.pop_front\>"
syn match   verilogMethod      "\.prev\>"
syn match   verilogMethod      "\.product\>"
syn match   verilogMethod      "\.purge\>"
syn match   verilogMethod      "\.push_back\>"
syn match   verilogMethod      "\.push_front\>"
syn match   verilogMethod      "\.put\>"
syn match   verilogMethod      "\.putc\>"
syn match   verilogMethod      "\.rand_mode\>"
syn match   verilogMethod      "\.realtoa\>"
syn match   verilogMethod      "\.resume\>"
syn match   verilogMethod      "\.reverse\>"
syn match   verilogMethod      "\.rsort\>"
syn match   verilogMethod      "\.self\>"
syn match   verilogMethod      "\.set\>"
syn match   verilogMethod      "\.shuffle\>"
syn match   verilogMethod      "\.size\>"
syn match   verilogMethod      "\.sort\>"
syn match   verilogMethod      "\.start\>"
syn match   verilogMethod      "\.status\>"
syn match   verilogMethod      "\.stop\>"
syn match   verilogMethod      "\.substr\>"
syn match   verilogMethod      "\.sum\>"
syn match   verilogMethod      "\.suspend\>"
syn match   verilogMethod      "\.swap\>"
syn match   verilogMethod      "\.tolower\>"
syn match   verilogMethod      "\.toupper\>"
syn match   verilogMethod      "\.try_get\>"
syn match   verilogMethod      "\.try_peek\>"
syn match   verilogMethod      "\.try_put\>"
syn match   verilogMethod      "\.unique\>"
syn match   verilogMethod      "\.unique_index\>"
syn match   verilogMethod      "\.xor\>"

syn match   verilogAssertion   "\<\w\+\>\s*:\s*\<assert\>\_.\{-});"

"-------------------------------------------------------------------------------
" UVM
"syn match   uvmClass           "\<uvm_\w\+\>"
"syn match   uvmClass           "\<uvm_tlm_\w\+\>"
"syn keyword uvmClass             
"syn keyword uvmMethod            
"syn keyword uvmMethodGlobal      
"syn keyword uvmDeprecatedMethod  

"-------------------------------------------------------------------------------
" uvm

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