module kz(
input clk ,
input key_stop ,
input key_choose ,
input key_vga ,
input rs232_signal,
input uart_set_choose_en, // 串口设置使能
input [2:0] uart_choose_set, // 串口设置值
output reg [1:0] mode ,
output reg stop ,
output reg [2:0] choose
);
always@(posedge clk)
begin
if(key_stop)begin
stop <= 0;
end else begin
stop <= 1;
end
end
always@(posedge clk or posedge rs232_signal )
begin
// 优先级1: 串口直接设置
if (uart_set_choose_en) begin
choose <= uart_choose_set;
end
// 优先级2: 物理按键切换
else if (stop && key_choose) begin
if (choose == 3'd5)
choose <= 0;
else
choose <= choose + 1;
end
end
always @(posedge clk)
begin
if (key_vga) begin
if (mode == 2'd2)
mode <= 0;
else
mode <= mode + 1;
end
end
endmodule module vga_colorbar (
input wire sys_clk, // 输入系统时钟，50MHz
input wire sys_rst_n, // 系统复位信号，低电平有效
input wire key, //按键输入信号
input wire shift, //按键输入信号
output wire hsync, // 行同步信号
output wire vsync, // 场同步信号
output wire [2:0] rgb, // 输出RGB像素数据
input key_stop ,
input key_choose ,
input key_add ,
input rx,
output beep ,
output [3:0] data0 ,
output [3:0] data1 ,
output [3:0] data2 ,
output [3:0] data3 ,
output [3:0] data4 ,
output [3:0] data5 ,
output led0,
output led1,
output tx
);
wire vga_clk; // VGA工作时钟，25MHz
wire locked; // PLL锁定信号
wire rst_n; // 复位信号
wire [9:0] pix_x; // 像素X轴坐标
wire [9:0] pix_y; // 像素Y轴坐标
wire [2:0] pix_data; // 像素数据
wire [1:0]mode; // 显示模式选择信号
//wire [5:0] seconds; // 秒
//wire [5:0] minutes; // 分钟
//wire [4:0] hours; // 小时
wire clk_8hz;
wire stop ;
wire [2:0] choose ;
wire flag_1s;
wire [5:0] second;
wire [5:0] minute;
wire [4:0] hour ;
wire [5:0] alarm_second;
wire [5:0] alarm_minute;
wire [4:0] alarm_hour ;
wire beeps;
wire [3:0] da0;
wire [3:0] da1;
wire [3:0] da2;
wire [3:0] da3;
wire [3:0] da4;
wire [3:0] da5;
wire [7:0] po_data;
wire po_flag;
parameter UART_BPS = 14'd9600; //比特率
parameter CLK_FREQ = 26'd50_000_000; //时钟频率
// 新增串口控制信号
wire [2:0] uart_choose_set;
wire uart_set_choose_en, uart_key_add_pulse, uart_shift_pulse;
wire key_add_combined, shift_combined;
// 125ms脉冲展宽器
reg [24:0] stretch_cnt = 0; // 50MHz下125ms计数(6_250_000)
reg stretch_en = 0;
reg [2:0] cmd_choose_buf;
reg cmd_add_buf = 0;
reg cmd_shift_buf = 0;
assign rst_n = sys_rst_n & locked;
// 串口指令解析
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
stretch_en <= 0;
cmd_choose_buf <= 0;
cmd_add_buf <= 0;
cmd_shift_buf <= 0;
end else begin
// 检测串口数据有效且处于设置模式
if (po_flag && !key_stop) begin
case (po_data)
8'd0, 8'd1, 8'd2, 8'd3, 8'd4, 8'd5: begin
cmd_choose_buf <= po_data[2:0];
cmd_add_buf <= 0;
cmd_shift_buf <= 0;
stretch_en <= 1;
stretch_cnt <= 0;
end
8'd6: begin
cmd_choose_buf <= 0;
cmd_add_buf <= 1;
cmd_shift_buf <= 0;
stretch_en <= 1;
stretch_cnt <= 0;
end
8'd7: begin
cmd_choose_buf <= 0;
cmd_add_buf <= 0;
cmd_shift_buf <= 1;
stretch_en <= 1;
stretch_cnt <= 0;
end
default: ; // 忽略无效指令
endcase
end
// 脉冲展宽控制
else if (stretch_en) begin
if (stretch_cnt == 25'd6_249_999) begin // 125ms
stretch_en <= 0;
end else begin
stretch_cnt <= stretch_cnt + 1;
end
end
end
end
// 生成展宽后的控制信号
assign uart_choose_set = cmd_choose_buf;
assign uart_set_choose_en = stretch_en && (|cmd_choose_buf);
assign uart_key_add_pulse = stretch_en && cmd_add_buf;
assign uart_shift_pulse = stretch_en && cmd_shift_buf;
// 合并物理按键和串口信号
assign key_add_combined = key_add || uart_key_add_pulse;
assign shift_combined = shift || uart_shift_pulse;
// PLL时钟生成模块
clk_gen clk_gen_inst (
.areset(~sys_rst_n),
.inclk0(sys_clk),
.c0(vga_clk),
.locked(locked)
);
// VGA控制模块
vga_ctrl vga_ctrl_inst (
.vga_clk(vga_clk),
.sys_rst_n(rst_n),
.pix_data(pix_data),
.pix_x(pix_x),
.pix_y(pix_y),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb)
);
// 按键控制模块
//key_control key_control_inst (
// .clk(clk_8hz),
// .key(key),
// .mode(mode)
//);
// 实例化时钟生成模块
//clock_gen u_clock_gen (
// .clk(sys_clk),
// .reset(rst_n),
// .seconds(seconds),
// .minutes(minutes),
// .hours(hours)
//);
// 生成模块
vga_pic vga_pic_inst (
.vga_clk(vga_clk),
.sys_rst_n(rst_n),
.pix_x(pix_x),
.pix_y(pix_y),
.mode(mode),
.pix_data_out(pix_data),
.hr_units(data1),
.hr_tens(data0),
.min_tens(data2),
.min_units(data3),
.sec_tens(data4),
.sec_units(data5)
);
clk_8hz clk_8hz_0
(
.clk(sys_clk),
.clk_8hz(clk_8hz)
);
// 按键控制模块
kz kz_0(
.clk (clk_8hz),
.key_stop (key_stop),
.key_choose (key_choose),
.key_vga (key),
.uart_set_choose_en (uart_set_choose_en), // 新增
.uart_choose_set (uart_choose_set), // 新增
.mode (mode),
.stop (stop),
.choose (choose)
);
clk_1s clk_1s_0(
.clk (clk_8hz ), //input clk ,
.stop (stop ), //input stop ,
.flag_1s (flag_1s) //output flag_1s
);
clock clock_0(
.clk (clk_8hz ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.flag_add (key_add ), //input flag_add ,
.flag_1s (flag_1s ), //input flag_1s ,
.second (second ), //output reg [5:0] second ,
.minute (minute ), //output reg [5:0] minute ,
.hour (hour ) //output reg [4:0] hour
);
alarm_clock alarm_clock_0(
.clk (clk_8hz ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.flag_add (key_add_combined), // 使用合并信号 //input flag_add ,
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.alarm_second (alarm_second ), //output reg [5:0] alarm_second ,
.alarm_minute (alarm_minute ), //output reg [5:0] alarm_minute ,
.alarm_hour (alarm_hour ), //output reg [4:0] alarm_hour ,
.beep (beeps ) //output beep
);
digital_display digital_display_0(
.clk (sys_clk ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.shift (shift_combined), // 使用合并信号
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.alarm_second (alarm_second), //input [5:0] alarm_second ,
.alarm_minute (alarm_minute), //input [5:0] alarm_minute ,
.alarm_hour (alarm_hour ), //input [4:0] alarm_hour ,
.data0 (data0 ), //output reg [3:0] data0 ,
.data1 (data1 ), //output reg [3:0] data1 ,
.data2 (data2 ), //output reg [3:0] data2 ,
.data3 (data3 ), //output reg [3:0] data3 ,
.data4 (data4 ), //output reg [3:0] data4 ,
.data5 (data5 ), //output reg [3:0] data5
.led0 (led0),
.led1 (led1)
);
digital_display digital_display_1(
.clk (sys_clk ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.shift (shift ),
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.alarm_second (alarm_second), //input [5:0] alarm_second ,
.alarm_minute (alarm_minute), //input [5:0] alarm_minute ,
.alarm_hour (alarm_hour ), //input [4:0] alarm_hour ,
.data0 (da0 ), //output reg [3:0] data0 ,
.data1 (da1 ), //output reg [3:0] data1 ,
.data2 (da2 ), //output reg [3:0] data2 ,
.data3 (da3 ), //output reg [3:0] data3 ,
.data4 (da4 ), //output reg [3:0] data4 ,
.data5 (da5 ) //output reg [3:0] data5
);
beep beep_0(
.sys_clk (sys_clk ), //input clk ,
.sys_rst_n (key ), //input key_rt ,
.stop (stop ), //input stop ,
.beep (beeps ), //input beep ,
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.ring (beep ), //output ring ,
.flag_1s (flag_1s ) //output flag_1s ,
);
uart_rx
#(
.UART_BPS (UART_BPS), //串口波特率
.CLK_FREQ (CLK_FREQ) //时钟频率
)
uart_rx_inst
(
.sys_clk (sys_clk ), //input sys_clk
.sys_rst (!key_stop ), //input sys_rst_n
.rx (rx ), //input rx
.po_data (po_data ), //output [7:0] po_data
.po_flag (po_flag ) //output po_flag
);
uart_tx
#(
.UART_BPS (UART_BPS), //串口波特率
.CLK_FREQ (CLK_FREQ) //时钟频率
)
uart_tx_inst
(
.sys_clk (sys_clk ), //input sys_clk
.sys_rst (!key_stop ), //input sys_rst_n
.pi_data (po_data ), //input [7:0] pi_data
.pi_flag (po_flag ), //input pi_flag
.tx (tx ) //output tx
);
endmodule
Error (10200): Verilog HDL Conditional Statement error at kz.v(28): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct Error: Can't elaborate user hierarchy "kz:kz_0"上面的功能不做任何改变，新增功能也不改变修复这个错误
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本文介绍了一个常见的Verilog编译错误：在用户定义的层次结构中无法进行编译。该错误通常发生在if-else语句中，当if后没有正确跟随else时会触发此错误。文章通过一个具体的例子说明了如何避免这个问题。
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