【视频】Device Partner平台第3期:开发阶段如何创建及定义产品

鸿蒙智联:开发阶段产品创建与定义指南
本文档详细介绍了DevicePartner在开发阶段创建和定义产品时所需填写的信息,包括如何选择软硬件规格。欲了解更多详情,请访问DevicePartner官网获取鸿蒙智联智能硬件生态合作伙伴计划的详细指导文档。

DevicePartner第3期:开发阶段如何创建及定义产品

详细介绍伙伴在开发阶段创建及定义产品时需填写的信息,如何选择软硬件规格等。

想了解更多内容请访问Device Partner官网:HarmonyOS Connect-鸿蒙智联智能硬件生态
加入合作伙伴计划详细指导文档:文档中心

Determining the location of the ModelSim executable... Using: d:/intelfpga_lite/18.1/modelsim_ae/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off lab1 -c lab1 --vector_source="G:/intelFPGA_lite/project/DL2236115315/Waveform.vwf" --testbench_file="G:/intelFPGA_lite/project/DL2236115315/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sat May 03 21:34:39 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off lab1 -c lab1 --vector_source=G:/intelFPGA_lite/project/DL2236115315/Waveform.vwf --testbench_file=G:/intelFPGA_lite
05-04
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