introduce HDL and give some examples about the Verilog language

本文介绍了硬件描述语言(HDL)的概念及两种主要风格:Verilog和VHDL,并详细阐述了Verilog的两种模块描述方式——结构描述和行为描述,包括使用逻辑表达式和过程语句的方法。

1. Overview of HDLs

    HDL is hardware description language is means that it is a language to describe hardware. 

HDLs have two main styles: Verilog and VHDL.  Verilog: is C-based and VHDL is Ada based.  Those days, Verilog is mainly used in electronic and industry owing to the programming is based on C language. 

2. two different ways to specific the modules

    Structural and Behavioral.

  Figure 1

  Structural : first it represent the simple element then connect those elements together.
   For example: for figure 1
------------------------------------------------------------------
   module figure1(x1,x2,x3,f);
input x1,x2,x3
output f;

and(g,x1,x2);
not (k,x2);
and(h,k,x3);
or(f,g,h);

endmodule
  --------------------------------------------------------------------- 
 When represent large circuits, we should use Behavioral which still has two types: logic expression and procedural statements.
for logic expression:  the statements are concurrent
------------------------------------------------------------------------
      module figure1(x1,x2,x3,f);
input x1,x2,x3;
output f;
assign f=(x1 & x2)|(~x2 & x3);

endmodule
-------------------------------------------------------------------------
for procedural statements: the statments should access in order, so it need always block 
-------------------------------------------------------------------------
module figure1(x1,x2,x3,f);
input x1,x2,x3;
output f;
reg f;
always @(x1 or x2 or x3)
if(x2==1)
f=x1;
else
f=x3;
endmodule
-------------------------------------------------------------------------














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