module yinsong (RST,CLK,CNT);
input RST, CLK;
output [3:0] CNT;
reg [3:0] CNT;
integer CNT_MAX = 6;
always @ (posedge CLK or posedge RST)
begin
if(RST)
CNT = 0;
else if(CNT < CNT_MAX)
begin
CNT = CNT + 1'b1;
end
else
begin
CNT = 0;
if(CNT_MAX < 9)
CNT_MAX = CNT_MAX + 1;
else
CNT_MAX = 6;
end
end
endmodule