<2133790> /*0x1e00b41e[04]*/ movi@agx a4,0x13524
vliw_cnt = 0x1e2a05
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468252
cyc = 0x325cbf00
esl_cyc = ac4b78
lla_mode = 0x0
a4 = 0x13524 { 0xffffffee }
<2133791> /*0x1e00b422[04]*/ l32i@agl a27,a27,0x8
vliw_cnt = 0x1e2a06
load transId_A = 0x10478f8003
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468252
cyc = 0x325cbf01
esl_cyc = ac4b79
load_cyc_A = 3
lla_mode = 0x0
a27 = 0xf4008650 { 0xf2605dc0 }
<thread0><RD-trn:0x10478f8003>[cacheable][shareable]<data A><2133791> read mem [0xf2605dc8] [4] = f4 00 86 50
<2133792> /*0x1e00b426[04]*/ {c.add.i.sp@agx a5,0x10; c.mov@agx a4,a26}
vliw_cnt = 0x1e2a07
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468252
cyc = 0x325cbf02
esl_cyc = ac4b7a
lla_mode = 0x0
a5 = 0xf00ffe30 { 0x6 }
a4 = 0xf2500000 { 0x13524 }
<2133793> /*0x1e00b42a[02]*/ c.callx0@pcu a27
vliw_cnt = 0x1e2a08
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468252
cyc = 0x325cbf03
esl_cyc = ac4b7b
lla_mode = 0x0
a30 = 0x1e00b42c { 0x1e00b416 }
<2133794> /*0xf4008650[14]*/ {c.addspi@agx -0x60; s64i.sp@ags a24:a25,-0x28; c.tsteqz@agx sr_t1,a5; movi32@agx a2,0xf2701a10}
vliw_cnt = 0x1e2a09
load transId_A = -0x1
load transId_B = -0x1
store transId_A = 0x1047910002
store transId_B = -0x1
fsId = 2468255
cyc = 0x325cbf04
esl_cyc = ac4b7c
lla_mode = 0x0
sp = 0xf00ffdc0 { 0xf00ffe20 }
ssp = 0xf00ffdc0 { 0xf00ffe20 }
- sr_t1 = 0x0
a2 = 0xf2701a10 { 0x3048a948 }
<thread0><WR-trn:0x1047910002>[cacheable][non-shareable]<data A><2133794> write mem [0xf00ffdf8] [8] = 00 00 00 00 00 00 00 00
<2133795> /*0xf400865e[14]*/ {l16ui@agl a3,a2,0x0; c.s64i.sp@ags a22:a23,0x30; movi32@agx a25,0x600000f2; c.mov@agx a24,a4}
vliw_cnt = 0x1e2a0a
load transId_A = 0x1047918003
load transId_B = -0x1
store transId_A = 0x1047918002
store transId_B = -0x1
fsId = 2468256
cyc = 0x325cbf05
esl_cyc = ac4b7d
load_cyc_A = 3
lla_mode = 0x0
a25 = 0x600000f2 { 0x0 }
a24 = 0xf2500000 { 0x0 }
a3 = 0x400 { 0x3048a948 }
<thread0><RD-trn:0x1047918003>[cacheable][non-shareable]<data A><2133795> read mem [0xf2701a10] [2] = 04 00
<thread0><WR-trn:0x1047918002>[cacheable][non-shareable]<data A><2133795> write mem [0xf00ffdf0] [8] = 32 5c b2 73 00 00 00 90
<2133796> /*0xf400866c[04]*/ {c.mov@agx a22,a5; c.s64i.sp@ags a26:a27,0x40}
vliw_cnt = 0x1e2a0b
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = 0x1047920004
fsId = 2468256
cyc = 0x325cbf06
esl_cyc = ac4b7e
lla_mode = 0x0
a22 = 0xf00ffe30 { 0x90 }
<thread0><WR-trn:0x1047920004>[cacheable][non-shareable]<data B><2133796> write mem [0xf00ffe00] [8] = f4 00 86 50 f2 50 00 00
#=Stall=# cyc = 0x325cbf07: load need stall due to dcc miss, mnemo: [!t1]l32il.cond@agl a21,a22,0x0, instanceId: 2133797, stalled load transId: 0x1047928003, cacheable, bus: 0x1, dcc state: DCC_STATE_BANK
#=Stall=# cyc = 0x325cbf08: load need stall due to dcc miss, mnemo: [!t1]l32il.cond@agl a21,a22,0x0, instanceId: 2133797, stalled load transId: 0x1047928003, cacheable, bus: 0x1, dcc state: DCC_STATE_BANK
#=Stall=# cyc = 0x325cbf09: load need stall due to dcc miss, mnemo: [!t1]l32il.cond@agl a21,a22,0x0, instanceId: 2133797, stalled load transId: 0x1047928003, cacheable, bus: 0x1, dcc state: DCC_STATE_BANK
#=Stall=# cyc = 0x325cbf0a: load need stall due to dcc miss, mnemo: [!t1]l32il.cond@agl a21,a22,0x0, instanceId: 2133797, stalled load transId: 0x1047928003, cacheable, bus: 0x1, dcc state: DCC_STATE_HIT
<2133797> /*0xf4008670[12]*/ {[!t1]l32il.cond@agl a21,a22,0x0; c.s32i.sp@ags a30,0x50; moviu8sft@agx a26,0x7d,0x10}
vliw_cnt = 0x1e2a0c
load transId_A = 0x1047928003
load transId_B = -0x1
store transId_A = 0x1047928002
store transId_B = -0x1
fsId = 2468257
cyc = 0x325cbf0b
esl_cyc = ac4b83
latency = 0x4
load_cyc_A = 7
lla_mode = 0x0
a26 = 0x7d0000 { 0xf2500000 }
a21 = 0x7 { 0xfffffc00 }
<thread0><RD-trn:0x1047928003>[cacheable][non-shareable]<data A><2133797> read mem [0xf00ffe30] [4] = 00 00 00 07
<thread0><WR-trn:0x1047928002>[cacheable][non-shareable]<data A><2133797> write mem [0xf00ffe10] [4] = 1e 00 b4 2c
CORE_NUM_PREDICTABLE_COF tp = 1 btbState : 4
<2133798> /*0xf400867c[06]*/ {[t1]c.b.cond@pcu 0xf4008784,0; c.tstneqz@agxl sr_t0,a21; c.s64i.sp@ags a28:a29,0x48}
vliw_cnt = 0x1e2a0d
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = 0x1047930004
fsId = 2468258
cyc = 0x325cbf0c
esl_cyc = ac4b84
lla_mode = 0x0
- sr_t0 = 0x1
<thread0><WR-trn:0x1047930004>[cacheable][non-shareable]<data B><2133798> write mem [0xf00ffe08] [8] = 00 00 00 00 00 00 00 01
CORE_NUM_PREDICTABLE_COF tp = 1 btbState : 4
<2133799> /*0xf4008682[08]*/ {[!t0]c.b.cond@pcu 0xf4008784,0; [t0]l32il.cond@agl a1,a22,0x8}
vliw_cnt = 0x1e2a0e
load transId_A = 0x1047938003
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468258
cyc = 0x325cbf0d
esl_cyc = ac4b85
load_cyc_A = 6
lla_mode = 0x0
a1 = 0x900500 { 0x0 }
<thread0><RD-trn:0x1047938003>[cacheable][non-shareable]<data A><2133799> read mem [0xf00ffe38] [4] = 00 90 05 00
<2133800> /*0xf400868a[04]*/ srli@agxl a23,a1,0x10
vliw_cnt = 0x1e2a0f
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468258
cyc = 0x325cbf0e
esl_cyc = ac4b86
lla_mode = 0x0
a23 = 0x90 { 0x325cb273 }
CORE_NUM_PREDICTABLE_COF tp = 1 btbState : 4
<2133801> /*0xf400868e[08]*/ {[t1]c.b.cond@pcu 0xf40087ae,1; tstgeu@agxl sr_t1,a23,a3; c.mov@agxl a4,a23}
vliw_cnt = 0x1e2a10
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468259
cyc = 0x325cbf0f
esl_cyc = ac4b87
lla_mode = 0x0
- sr_t1 = 0x0
a4 = 0x90 { 0xf2500000 }
CORE_NUM_PREDICTABLE_COF tp = 3 btbState : 0
<2133802> /*0xf4008696[12]*/ {call0@pcu 0xf5006ee0; movi32@agx a25,0x60000600}
vliw_cnt = 0x1e2a11
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468260
cyc = 0x325cbf10
esl_cyc = ac4b88
lla_mode = 0x0
a30 = 0xf40086a2 { 0x1e00b42c }
a25 = 0x60000600 { 0x600000f2 }
#=Stall=# cyc = 0x325cbf11: RAW hazard between a4 write on M by 'c.mov@agxl a4,a23' and a4 read on E by 'slli@agx a14,a4,1'
<2133803> /*0xf5006ee0[10]*/ {movi32@agx a12,0xf2701a10; slli@agx a14,a4,1}
vliw_cnt = 0x1e2a12
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468263
cyc = 0x325cbf12
esl_cyc = ac4b8a
latency = 0x1
lla_mode = 0x0
a12 = 0xf2701a10 { 0x1 }
a14 = 0x120 { 0x0 }
<2133804> /*0xf5006eea[04]*/ l32i@agl a13,a12,0x8
vliw_cnt = 0x1e2a13
load transId_A = 0x1047960003
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468263
cyc = 0x325cbf13
esl_cyc = ac4b8b
load_cyc_A = 3
lla_mode = 0x0
a13 = 0xf26008a0 { 0x3f }
<thread0><RD-trn:0x1047960003>[cacheable][non-shareable]<data A><2133804> read mem [0xf2701a18] [4] = f2 60 08 a0
<2133805> /*0xf5006eee[02]*/ c.tsteqz@agxl sr_t0,a13
vliw_cnt = 0x1e2a14
load transId_A = -0x1
load transId_B = -0x1
store transId_A = -0x1
store transId_B = -0x1
fsId = 2468263
cyc = 0x325cbf14
esl_cyc = ac4b8c
lla_mode = 0x0
sr_t0 = 0x0 { 0x1 }
#=Stall=# cyc = 0x325cbf15: LoadToLoadUse: RAW hazard between a13 write on M by 'l32i@agl a13,a12,0x8' and a13 read on E by '[!t0]l16u.x.cond@agl a15,a13,a14'
#=Stall=# cyc = 0x325cbf16: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf17: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf18: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf19: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf1a: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf1b: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf1c: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf1d: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf1e: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf1f: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf20: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf21: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf22: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC
#=Stall=# cyc = 0x325cbf23: load need stall due to dcc miss, mnemo: [!t0]l16u.x.cond@agl a15,a13,a14, instanceId: 2133806, stalled load transId: 0x1047970003, cacheable, bus: 0x1, dcc state: DCC_STATE_MB_ALLOC这些指令是什么意思