提示：本文为第一个章节
数字全流程设计记录——基于S40ll工艺
背景
本文记录一个混合信号IC设计中的数字模块设计全流程，及数模混合验证流程。采用工艺为s40ll，设计为连续时间Sigma Delta调制器，数字部分包括调制器中的环路滤波器，及外围的SPI模块。
数字模块为verilog语言，采用vcs+verdi进行编译和仿真，采用dc进行逻辑综合，采用innovus进行布局布线，采用calibre进行布局后验证，采用ic618+xcelium+spectre21.1进行AMS仿真和前后仿真。
服务器：SIC-C1集群服务器
Nickname: tara
1. 路径设置
数字流程为编译(compile)、综合(synthesis)、（形式化验证,formality）、布局布线(placement and routing)。其中布局布线包括数据初始化(data_init)、整体布局(floorplan)、电源布局(powerplan)、标准单元布局(placement)、时钟树(cts)、时钟树布局后优化(post_cts_opt)、布线(routing)、布线优化(routing_opt)、插入filler(chip_done)、版图导出(stream_out)。
1.1 路径原则
全部的数字设计均在同一个$(FLOW_HOME)下，细分文件夹为【designs】、【doc】、【result】、【scripts】、【sim】。其中【designs】文件夹下包含所有的数字项目用于综合和布局布线所需要的所有的文件，包括源代码【src】、工艺库【pdk】等；【result】和【sim】仅保存当前设计的结果，下分文件夹包括编译【cmpl】、综合【syn】和布局布线【pr】。
1.2 具体路径
本设计所在的路径为 “/home/usrname/project/~”
Digital (FLOW_HOME)
Makefile //run scripts
designs
src //design related file
tara //nickname
DIG_w_DWA.v //design source code
DIG_w_DWA_tb.tb
othernickname
smic40ll //design plateform
tara
config.mk //verilog code configuration files
constraint.sdc //synopsys design constraints
constraint_for_pr.sdc
DIG_w_DWA.io //io placement file
pdk
config.mk //synthesis and placement and routing configuration files
smic40ll //digital lib and pr kit
sc12mc_base_lvt_c50 // standard digital cell lib
arm-routing-kit //PDK routing metal layer information
doc //screenshots for steps results
result
cmpl //compile results
syn //synthesis results
pr //placement and routing results
scripts
syn //synthesis scripts
fml //formality scripts
pr //placement and routing results
sim
cmpl //RTL compile
syn //RLT codes synthesis
pr //place and route simulation
1.3 Makefile
【Makefile】 中规定各个流程所需要运行的脚本文件，如下所示：
# pwd = /home/usrname/project/$(FLOW_HOME)/~
# Dir variable
export FLOW_HOME ?= /home/usrname/Project/Digital
export DESIGN_HOME ?= $(FLOW_HOME)/designs
export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts
export RESULT_DIR ?= $(FLOW_HOME)/result
# Design config
DESIGN_CONFIG ?= ./designs/smic40ll/tara/config.mk
# Process config
PDK_CONFIG ?= ./designs/smic40ll/pdk/config.mk
include $(DESIGN_CONFIG)
include $(PDK_CONFIG)
# Synthesis Corner
export WCORNER = ss_typical_max_0p99v_125c
export BCORNER = tt_typical_max_1p10v_25c
#Flow optin
#synthesis
syn:
cd $(RESULT_DIR); mkdir -p syn/data; \
mkdir -p syn/log; \
mkdir -p syn/report; \
mkdir -p syn/work; \
mkdir -p scanchain/data; \
mkdir -p scanchain/report; \
mkdir -p scanchain/log
@echo "Current Corner is" $(WCORNER)
design_vision &
dc_shell -f -64 $(SCRIPTS_DIR)/syn/dc_main.tcl | tee $(RESULT_DIR)/syn/log/syn.log
#formality verification
fml_syn:
cd $(RESULT_DIR); mkdir -p fml_syn/data; \
mkdir -p fml_syn/log; \
mkdir -p fml_syn/report; \
mkdir -p fml_syn/work
fm_shell -64 -f $(SCRIPTS_DIR)/fml/fml_main.tcl \
-work_path $(RESULT_DIR)/fml_syn/work \
| tee $(RESULT_DIR)/fml_syn/report/fml.log
#placement and routing
data_init:
cd $(RESULT_DIR); mkdir -p pr/data; \
mkdir -p pr/log; \
mkdir -p pr/report;
innovus -files $(SCRIPTS_DIR)/pr/init.tcl \
-log "$(RESULT_DIR)/pr/log/init" -overwrite
@echo "Finish data_init"
floorplan:
innovus -files $(SCRIPTS_DIR)/pr/floor_plan.tcl \
-log "$(RESULT_DIR)/pr/log/floorplan" -overwrite
@echo "Finish Floor_plan"
powerplan:
innovus -files $(SCRIPTS_DIR)/pr/power_plan.tcl \
-log "$(RESULT_DIR)/pr/log/power_plan" -overwrite
@echo "Finish Power_plan"
placement:
innovus -files $(SCRIPTS_DIR)/pr/placement.tcl \
-log "$(RESULT_DIR)/pr/log/placement" -overwrite
@echo "Finish Placement"
cts:
innovus -files $(SCRIPTS_DIR)/pr/cts.tcl \
-log "$(RESULT_DIR)/pr/log/cts" -overwrite
@echo "Finish CTS"
post_cts_opt:
innovus -files $(SCRIPTS_DIR)/pr/post_cts_opt.tcl \
-log "$(RESULT_DIR)/pr/log/post_cts_opt" -overwrite
@echo "Finish CTS opt"
routing:
innovus -files $(SCRIPTS_DIR)/pr/routing.tcl \
-log "$(RESULT_DIR)/pr/log/routing" -overwrite
@echo "Finish Routing"
routing_opt:
innovus -files $(SCRIPTS_DIR)/pr/routing_opt.tcl \
-log "$(RESULT_DIR)/pr/log/routing_opt" -overwrite
@echo "Finish Routing opt"
chip_done:
innovus -files $(SCRIPTS_DIR)/pr/chip_done.tcl \
-log "$(RESULT_DIR)/pr/log/chip_done" -overwrite
@echo "Finish Chip_done"
stream_out:
innovus -files $(SCRIPTS_DIR)/pr/stream_out.tcl \
-log "$(RESULT_DIR)/pr/log/stream_out" -overwrite
@echo "Finish Stream_out"
run_pr:
${MAKE} data_init
${MAKE} floorplan
${MAKE} powerplan
${MAKE} placement
${MAKE} cts
${MAKE} post_cts_opt
${MAKE} routing
${MAKE} routing_opt
${MAKE} chip_done
${MAKE} stream_out
cdl_PG:
v2lvs -addpin VNW -addpin VPW -v $(RESULT_DIR)/pr/data/DIG_w_DWA_lvs.vg \
-o $(RESULT_DIR)/pr/data/DIG_w_DWA_PG.cdl \
-i \
-l $(DESIGN_HOME)/smic40ll/pdk/smic40_digilib/verilog/sc12mc_logic0040ll_base_lvt_c50_PG.v \
-lsp $(DESIGN_HOME)/smic40ll/pdk/smic40_digilib/cdl/sc12mc_logic0040ll_base_lvt_c50.cdl
2. 环境配置
数字综合的设计和工艺库通过config.mk文件进行配置。
2.1 设计配置
设计配置文件【config.mk】如下所示：
# pwd = /home/usrname/project/$(FLOW_HOME)/designs/smic40ll/tara/~
export DESIGN_NICKNAME = tara
export DESIGN_NAME = DIG_w_DWA
export PLATFORM = smic40ll
export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/DIG_w_DWA.v \
./designs/src/$(DESIGN_NICKNAME)/DIG_DWA.v \
./designs/src/$(DESIGN_NICKNAME)/DIG_THERMO.v \
添加综合和布线所需要的sdc约束文件和布局布线的io文件：
export PR_SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_for_pr.sdc
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
# export DEF_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).def
export IO_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).io
2.1.1 sdc文件
用于综合的时序约束文件【constraint.sdc】如下所示：
设置当前设计名、全局时钟名（用于设置约束）、时钟端口名（.v文件中的时钟端口名）、复位端口名（.v文件中的复位端口名）、时钟周期（单位为ns）、输入端口延迟（单位为ns）、输出端口延迟（单位为ns）。
deterio_ratio为时钟退化系数，为一个时钟周期中可用的时间比例；CLK_UNCERTAINTY为时钟不稳定性系数，表征时钟jitter的大小。HOLD_DELAY为输出最小保持时间系数。
# pwd = /home/usrname/project/$(FLOW_HOME)/designs/smic40ll/tara/~
current_design DIG_w_DWA
set clk_name core_clock
set clk_port_name clk
set clk_period 2.5 # ns
set deterio_ratio 1
set inport_delay -0.3 # ns, corresponds to circuits
set outport_delay 0.3 # ns
set CLK_UNCERTAINTY 0.05
set HOLD_DELAY 0.05
set rst_port_name rstn
创建时钟，并确定时钟的时序要求：
# create clock object and set uncertainty
set clk_port [get_ports $clk_port_name]
set rst_port [get_ports $rst_port_name]
create_clock -name $clk_name -period [expr $clk_period * $deterio_ratio] $clk_port
set_clock_uncertainty -setup [expr $clk_period * $CLK_UNCERTAINTY] $clk_port
set_clock_uncertainty -hold [expr $clk_period * $HOLD_DELAY] $clk_port
set_dont_touch_network $clk_port
确定非时钟输入端口的时序要求：
# set constraints on inputs
set non_clock_inputs [remove_from_collection [all_inputs] $clk_port]
set non_clock_rst_inputs [remove_from_collection $non_clock_inputs $rst_port]
#input_delay & transtion take 5% of period / fanout 40 /max cap foundary advised
set_input_delay -max $inport_delay -clock $clk_name $non_clock_rst_inputs -clock_fall
设置输入、输出的驱动能力和时序要求，driving_cell表示数字模块的输入驱动，load为输出驱动电容（单位为pF）
set_driving_cell -lib_cell INV_X4M_A12TL50 -pin Y $non_clock_inputs
#set constraints on outputs
set_load 0.05 [all_outputs]
set_output_delay -max $outport_delay -clock $clk_name [all_outputs]
set_output_delay -min [expr $clk_period * -$HOLD_DELAY] -clock $clk_name [all_outputs]
如果log中read sdc出现_sel5…等类型的错误，说明sdc文件中括号多加或者少加了。
为了简化后续布局布线的难度，综合所用的sdc文件通常比布线的更加严格。
2.1.2 io配置文件；
【DIG_w_DWA.io】用于规定数字版图中输入输出接口位置，在数字后端流程的floorplan中，摆放好对应io后，在terminal中输入指令：
saveIoFile -locations DIG_w_DWA.io
生成的io文件会保存在innovus的启动路径下，【DIG_w_DWA.io】如下所示：
# pwd = /home/usrname/project/$(FLOW_HOME)/designs/smic40ll/tara/~
###############################################################
# Generated by: Cadence Innovus 21.35-s114_1
# OS: Linux x86_64(Host ID node2)
# Generated on: Sun Sep 1 15:52:48 2024
# Design: DIG_w_DWA
# Command: saveIoFile -locations DIG_w_DWA.io
###############################################################
(globals
version = 3
io_order = default
)
(iopin
(top
(pin name="muxout[7]" offset=12.1100 layer=5 width=0.2300 depth=1.0000 )
(pin name="muxout[6]" offset=13.0900 layer=5 width=0.2300 depth=1.0000 )
(pin name="muxout[5]" offset=14.0700 layer=5 width=0.2300 depth=1.0000 )
(pin name="muxout[4]" offset=15.0500 layer=5 width=0.2300 depth=1.0000 )
(pin name="muxout[3]" offset=16.0300 layer=5 width=0.2300 depth=1.0000 )
(pin name="muxout[2]" offset=17.0100 layer=5 width=0.2300 depth=1.0000 )
(pin name="muxout[1]" offset=18.1300 layer=5 width=0.2300 depth=1.0000 )
(pin name="muxout[0]" offset=19.1100 layer=5 width=0.2300 depth=1.0000 )
)
(left
(pin name="rstn" offset=60 layer=4 width=0.2300 depth=1.0000 )
(pin name="clk" offset=59 layer=4 width=0.2300 depth=1.0000 )
)
(bottom
(pin name="tout[0]" offset=20.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[1]" offset=21.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[2]" offset=22.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[3]" offset=23.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[4]" offset=24.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[5]" offset=25.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[6]" offset=26.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[7]" offset=27.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[8]" offset=28.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[9]" offset=29.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[10]" offset=30.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[11]" offset=31.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[12]" offset=32.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[13]" offset=33.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="tout[14]" offset=34.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[0]" offset=35.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[1]" offset=36.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[2]" offset=37.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[3]" offset=38.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[4]" offset=39.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[5]" offset=40.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[6]" offset=41.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[7]" offset=42.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[8]" offset=43.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[9]" offset=44.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[10]" offset=45.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[11]" offset=46.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[12]" offset=47.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[13]" offset=48.000 layer=5 width=0.23000 depth=1.0000 )
(pin name="toutb[14]" offset=49.000 layer=5 width=0.23000 depth=1.0000 )
)
(right
(pin name="dwa_en" offset=60.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[7]" offset=48.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[6]" offset=47.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[5]" offset=46.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[4]" offset=45.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[3]" offset=44.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[2]" offset=43.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[1]" offset=42.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="tru_in_r[0]" offset=41.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="overflow_flag" offset=24.0000 layer=6 width=0.2300 depth=1.0000 )
(pin name="pointer[3]" offset=23.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="pointer[2]" offset=22.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="pointer[1]" offset=21.0000 layer=4 width=0.2300 depth=1.0000 )
(pin name="pointer[0]" offset=20.0000 layer=4 width=0.2300 depth=1.0000 )
)
)
修改pin的位置时，通过修改pin脚所在的边(top, left, right, bottom)，修改对应的offset，其中top和bottom的offset为到左侧边的距离，left和right的offset为到下侧边的距离。pin脚所在的金属层为layer，pin脚的宽度为width，pin脚的长度为depth。io文件如下图所示：
2.2 工艺库配置
makefile语法中“\”表示换行，连续的两行执行第一行的命令，因此如果是两次不同的指令不可以加“\”分隔，直接换行即可。综合时采用最差的corner进行综合，对应Makefile文件中的WCORNER。
db文件为综合时调用的文件，lib文件和lef为后端布局布线中使用的文件。
ccs_tn为CCSM 模型，即synopsys采用的 noise，power，timing于一体的lib，较为准确，对应文件规模较大。
工艺库配置文件如下所示：
# pwd = /home/usrname/project/$(FLOW_HOME)/designs/smic40ll/pdk/~
# Process node
export PROCESS = 40
# ./designs/smic40ll/pdk/smic40/sc12mc_base_lvt_c50/r0p2/sc12mc_logic0040ll_base_lvt_c50_ss_typical_max_0p99v_125c.lib
#-----------------------------------------------------
# PDK Dir
# ----------------------------------------------------
export PDK_NAME = sc12mc_logic0040ll
export PDK_DIR = $(DESIGN_HOME)/smic40ll/pdk/smic40ll/sc12mc_base_lvt_c50/r0p2
export ROUTE_DIR = $(DESIGN_HOME)/smic40ll/pdk/smic40ll/arm-routing-kit/smic/logic0040ll/arm_tech/r3p4
export LEF_PATH = $(ROUTE_DIR)/lef
export METAL_USED = 1P7M_1TM_ALPA2
export LIB_PATH = $(PDK_DIR)/lib-ccs-tn
export DB_PATH = $(PDK_DIR)/db-ccs-tn
export SDB_PATH = $(PDK_DIR)/sdb
export STD_NAME = sc12mc_logic0040ll_base_lvt_c50
#---------------------------------------------------
# Db: used in synthesis
#---------------------------------------------------
export DB_FILES = $(DB_PATH)/$(STD_NAME)_$(WCORNER).db_ccs_tn \
$(ADDITIONAL_DBS)
export SDB_FILES = $(SDB_PATH)/$(STD_NAME).sdb
#----------------------------------------------------
# Lef: used in pr
#----------------------------------------------------
export LEF_FILES = $(LEF_PATH)/$(METAL_USED)/sc12mc_tech.lef \
$(PDK_DIR)/lef/$(STD_NAME).lef \
# $(DESIGN_HOME)/smic40ll/tara/DIG_w_DWA.lef
export LEF_NAME = $(STD_NAME)
#----------------------------------------------------
# Lib used in pr
#----------------------------------------------------
export LIB_FILES_BC = $(LIB_PATH)/$(STD_NAME)_$(BCORNER).lib_ccs_tn
export LIB_FILES_WC = $(LIB_PATH)/$(STD_NAME)_$(WCORNER).lib_ccs_tn
export LIB_NAME = $(STD_NAME)_$(BCORNER)
由于db中无ANTENNA1的定义，因此设置为不使用的CELL。
FILL_CELL采用FILLCAP提高VDD到VSS的解耦。
PHYSICAL_CELLS为使用FILLCAP时所需要添加的物理单元，用于芯片版图导出。
TAP_CELL为阱接触，版图中需要添加丰富的阱接触，以避免LATCH_UP现象。
CAP_TABLE为提取寄生时所使用文件，根据使用的工艺选择，用于延迟分析。
# Dont use cells list
export DONT_USE_CELLS = ANTENNA1_A12TL50
# Define fill cells
export FILL_CELLS = FILL1_A12TL50 \
FILL2_A12TL50 \
FILLCAP4_A12TL50 \
FILLCAP8_A12TL50 \
FILLCAP16_A12TL50 \
FILLCAP32_A12TL50 \
FILLCAP64_A12TL50 \
FILLCAP128_A12TL50
export PHYSICAL_CELLS = FILL2_A12TL50\
FILLCAP4_A12TL50 \
FILLCAP8_A12TL50 \
FILLCAP16_A12TL50 \
FILLCAP32_A12TL50 \
FILLCAP64_A12TL50 \
FILLCAP128_A12TL50
# Define well-tap cells
export TAP_CELL_NAME = FILLTIE3_A12TL50
#Define tie cells
export TIEHI_CELL_AND_PORT = TIEHI_X1M_A12TL50
export TIELO_CELL_AND_PORT = TIELO_X1M_A12TL50
#Define the scan enable port
export SCAN_ENABLE_PORT = SE
#--------------------------------------------------------
# DataInit
#--------------------------------------------------------
export CAP_TABLE = $(ROUTE_DIR)/cadence_captable/$(METAL_USED)/RCMAX.captbl
用于布局布线中使用的指令:
PLACE_SITE规定了版图中的与工艺库匹配的最小单元的单位尺寸。
PLACE_DENSITY为版图的密度，考虑到满足时序要求的布局布线的难度，一般设置后端布局布线的密度不超过0.7。
RATIO为高与宽的比例。
CORE_MARGIN为内部数字标准单元到版图边缘的距离，单位为um，用于加Power Ring。
#--------------------------------------------------------
# Floorplan
# -------------------------------------------------------
export PLACE_SITE = $(PDK_NAME)
export PLACE_DENSITY = 0.65
export RATIO = 0.5
export CORE_MARGIN = 10
#--------------------------------------------------------
# IO placement
# -------------------------------------------------------
export IO_LAYER = M5
规定电源地端口的名字，规定电源地条所用的金属层，电源条的宽度（单位为um），电源条的间距，本设计中横向的电源条为M6，纵向的电源条为TM2。
#--------------------------------------------------------
# Power plan
# -------------------------------------------------------
export PWR_PORT = VDD
export GND_PORT = VSS
export V_STRIPE_METAL = TM2
export H_STRIPE_METAL = M6
export STRIPE_WIDTH = 3
export STRIPE_SPACING = 3
export STRIPE_DISTANCE = 15
export SROUTE_MIN_LAYER = M1(1)
export SROUTE_MAX_LAYER = M5(5)
#---------------------------------------------------------
# Place
# --------------------------------------------------------
export MIN_GLOBAL_ROUTE_LAYER = 2
export MAX_GLOBAL_ROUTE_LAYER = 5
规定生长时钟树采用的BUF和INV单元，金属层分别为M3~M5。规定走时钟线采用的最低/最高的金属层，本设计中分别为M3和M5。规定其他走线采用的金属层，为M2-M6。
# --------------------------------------------------------
# CTS
# -------------------------------------------------------
export CTS_BUF_CELL = BUF*
export CTS_INV_CELL = INV_X0P5B_A12TL50 \
INV_X1B_A12TL50 \
INV_X2B_A12TL50 \
INV_X3B_A12TL50 \
INV_X4B_A12TL50 \
INV_X5B_A12TL50 \
INV_X6B_A12TL50 \
INV_X7P5B_A12TL50 \
INV_X9B_A12TL50 \
INV_X11B_A12TL50 \
INV_X13B_A12TL50 \
INV_X16B_A12TL50 \
INV_X16M_A12TL50
#Set the routing non-default rule which are used for clk tree routing
export CTS_ROUTING_MUL = 2
export NDR_CTS_MIN_LAYER = M3
export NDR_CTS_MAX_LAYER = M5
#Set the routing metal which are used for clk tree routing
export CTS_ROUTING_LAYER_RANGE = 5 2
# ---------------------------------------------------------
# Route
# ---------------------------------------------------------
export MIN_ROUTING_LAYER = 2
export MAX_ROUTING_LAYER = 6
该部分在ic618中实现，未使用数字流程，此处仅列出供参考。
# ---------------------------------------------------------
# Chip Finish
# ---------------------------------------------------------
#Set the layer text num for adding PG net text when running lvs
export LAYER_TEXT_NUM = 137
export GDS_MAP_FILE = $(LEF_PATH)/$(METAL_USED)/tech.map
# ---------------------------------------------------------
# ExtraceRC
# ---------------------------------------------------------
export RCXT_RULES =
# ---------------------------------------------------------
# Drc
# ---------------------------------------------------------
export STDCELL_GDS = $(PDK_DIR)/gds2/$(STD_NAME).gds2
# ---------------------------------------------------------
# Lvs
# ---------------------------------------------------------
export STDCELL_SPICE = $(PDK_DIR)/cdl/$(STD_NAME).cdl
export STDCELL_NETLIST =
# ---------------------------------------------------------
# IR Drop
# ---------------------------------------------------------
export QRC_FILE =
export PWR_NETS_VOLTAGES = 0.9
export PWR_THRESHOLD = 0.85
export GND_NETS_VOLTAGES = 0.0
export GND_THRESHOLD = 0.05
export RAIL_ANALYSIS_TEMPERATURE = 85
总结
以上为本次设计中数字后端所需的全部配置文件，下个章节介绍使用综合、布局布线所需要的的tcl文件。
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