HDL—Verilog Language—Procedures—Priority encoder with casez

最新推荐文章于 2025-12-01 17:45:00 发布

原创最新推荐文章于 2025-12-01 17:45:00 发布 · 338 阅读

0 ·

CC 4.0 BY-SA版权

文章标签：

#fpga开发 #学习

HDLBits题目专栏收录该内容

41 篇文章

订阅专栏

文章讨论了在Verilog编程中，casez和casex语句的用法。casez语句在比较时忽略高阻值z，而casex不仅忽略z，还忽略不确定值x。显式指定优先级可以提高代码的可读性和减少错误。示例展示了如何在不同情况下使用这两种语句来处理输入位模式。

There is also a similar casex that treats both x and z as don't-care. I don't see much purpose to using it over casez.
The digit ? is a synonym for z. so 2'bz0 is the same as 2'b? 0

It may be less error-prone to explicitly specify the priority behaviour rather than rely on the ordering of the case items. For example, the following will still behave the same way if some of the case items were reordered, because any bit pattern can only match at most one case item:

还有一个类似的casex，它将x和z都视为无关紧要。我觉得用它来对付卡塞兹没什么意义。

数字?是z的同义词，所以2'bz0和2'b是一样的?0

显式指定优先级行为比依赖case项的顺序更不容易出错。例如，如果某些case项重新排序，下面的代码仍然会有相同的行为，因为任何位模式最多只能匹配一个case项:

casez语句用来处理不考虑高阻值z的比较过程

reg[3:0]state;
casez(state)
8'b???1: do1;
8'b??1?: do2;
8'b?1??: do3;
8'b1???: do4;
endcase

casex语句则将高阻值z和不定值都视为不必关心的情况

reg[3:0]state;
casex(state)
8'bxxx1: do1;
8'bxx1x: do2;
8'bx1xx: do3;
8'b1xxx: do4;
endcase

// synthesis verilog_input_version verilog_2001
module top_module (
    input [7:0] in,
    output reg [2:0] pos );
    always@(*)begin
        casez(in)
            8'bzzzzzzz1:pos <= 3'b000;
            8'bzzzzzz1z:pos <= 3'b001;
            8'bzzzzz1zz:pos <= 3'b010;
            8'bzzzz1zzz:pos <= 3'b011;
            8'bzzz1zzzz:pos <= 3'b100;
            8'bzz1zzzzz:pos <= 3'b101;
            8'bz1zzzzzz:pos <= 3'b110;
            8'b1zzzzzzz:pos <= 3'b111;
        endcase
    end
endmodule