HDL—Verilog Language—Basics—Four wires

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

a -> w        b -> x        b -> y        c -> z

The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. From outside the module, there are three input ports and four output ports.

创建一个具有3个输入和4个输出的模块，其行为类似于建立这些连接的导线：

a->w        b->x        b->y        c->z

下图说明了电路的每个部分如何对应于Verilog代码的每个位。从模块外部看，有三个输入端口和四个输出端口。

 按照图片把对应输出输入assign起来就行