调试双摄像头(ov5648+gc2145)

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已于 2024-12-27 11:27:28 修改

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分类专栏： RK3566调试记录文章标签：驱动开发

于 2024-11-29 16:47:40 首次发布

本文链接：https://blog.youkuaiyun.com/2201_75485092/article/details/144139905

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一、配置dts

根据规格书知道i2c地址，因为需要7位地址，0x6c、0x6d 右移一位得到地址为0x36

0x78、0x79右移一位得到地址为 0x3c。0x36是ov5648的地址，0x3c是gc2145的地址。

RK3566平台仅有一个标准物理mipi csi2 dphy,可以工作在full mode 和split mode两个模式, 拆分为csi2_dphy0/csi2_dphy1/csi2_dphy2三个逻辑dphy

Full Mode:
仅使用csi2_dphy0,csi2_dphy0与csi2_dphy1/csi2_dphy2互斥,不可同时使用;
data lane最大4 lanes;
最大速率2.5Gbps/lane;

Split Mode:
仅使用csi2_dphy1和csi2_dphy2, 与csi2_dphy0互斥,不可同时使用;
csi2_dphy1和csi2_dphy2可同时使用;
csi2_dphy1和csi2_dphy2各自的data lane最大是2 lanes;
csi2_dphy1对应物理dphy的lane0/lane1;
csi2_dphy2对应物理dphy的lane2/lane3;
最大速率2.5Gbps/lane

参考文章：https://www.cnblogs.com/wmc245376374/p/16371245.html

csi2_dphy对应的关系要结合原理图来配置，关系如下：

这组对应&csi2_dphy1 -> rkisp_vir0

这组对应csi2_dphy2 -> mipi_csi2 -> rkcif_mipi_lvds - > rkcif_mipi_lvds_sditf -> rkisp_vir1

整体代码如下：

&csi2_dphy_hw {
	status = "okay";
};

&csi2_dphy1 {
	status = "okay";

	/*
	 * dphy1 only used for split mode,
	 * can be used  concurrently  with dphy2
	 * full mode and split mode are mutually exclusive
	 */
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			dphy1_in: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&ov5648_out>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			dphy1_out: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&isp0_in>;
			};
		};
	};
};

&csi2_dphy2 {
	status = "okay";

	/*
	 * dphy2 only used for split mode,
	 * can be used  concurrently  with dphy1
	 * full mode and split mode are mutually exclusive
	 */
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			dphy2_in: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&gc2145_out>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			dphy2_out: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&mipi_csi2_input>;
			};
		};
	};
};

&mipi_csi2 {
        status = "okay";

            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                            reg = <0>;
                            #address-cells = <1>;
                            #size-cells = <0>;

                            mipi_csi2_input: endpoint@1 {
                                    reg = <1>;
                                    remote-endpoint = <&dphy2_out>;
                                    data-lanes = <1 2>;
                            };
                    };


                    port@1 {
                            reg = <1>;
                            #address-cells = <1>;
                            #size-cells = <0>;

                            mipi_csi2_output: endpoint@0 {
                                    reg = <0>;
                                    remote-endpoint = <&cif_mipi_in>;
                                    data-lanes = <1 2>;
                            };
                    };
            };
};

&rkcif {
        status = "okay";
    };

&rkcif_mipi_lvds {
            status = "okay";
            port {
                    cif_mipi_in: endpoint {
                            remote-endpoint = <&mipi_csi2_output>;
                            data-lanes = <1 2>;
                    };
            };
};

&rkcif_mipi_lvds_sditf {
            status = "okay";
            port {
                    mipi_lvds_sditf: endpoint {
                            remote-endpoint = <&isp1_in>;
                            data-lanes = <1 2>;
                     };
            };
};

&rkisp {
	status = "okay";
};

&rkisp_mmu {
	status = "okay";
};

&rkisp_vir0 {
	status = "okay";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		isp0_in: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&dphy1_out>;
		};
	};
};

&rkisp_vir1 {
	status = "okay";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		isp1_in: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&mipi_lvds_sditf>;
		};
	};
};

ov5648: ov5648@36 {
		status = "okay";
		compatible = "ovti,ov5648";
		reg = <0x36>;
		clocks = <&cru CLK_CAM0_OUT>; // 这个要查看原理图是哪个clk
		//clocks = <&cru CLK_CIF_OUT>;
		clock-names = "xvclk";
		avdd-supply = <&vcc2v8_dvp>; // 这三个电源查看原理图
		dovdd-supply = <&vcc1v8_dvp>;
		dvdd-supply = <&vcc1v8_dvp>;
		power-domains = <&power RK3568_PD_VI>;
		pinctrl-names = "default";
		pinctrl-0 = <&cif_clk1>, <&gc_reset_gpio>, <&gc_pwdn_gpio>; //<&power_gpio>
		//reset pin control by hardware,used this pin switch to mipi input
		//1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera
		reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
		pwdn-gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
		//power-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "LMM248";//THDS11073
		rockchip,camera-module-lens-name = "YXC-M804A2"; //Largan-40122a1
		port {
			ov5648_out: endpoint {
				remote-endpoint = <&dphy1_in>;
				data-lanes = <1 2>;
			};
		};
	};

gc2145: gc2145@3c {
		status = "okay";
		compatible = "galaxycore,gc2145";
		reg = <0x3c>;
		//clocks = <&cru CLK_CAM0_OUT>;
		clocks = <&cru CLK_CIF_OUT>;
		clock-names = "xvclk";
		avdd-supply = <&vcc2v8_dvp>;
		dovdd-supply = <&vcc1v8_dvp>;
		dvdd-supply = <&vcc1v8_dvp>;
		power-domains = <&power RK3568_PD_VI>;
		pinctrl-names = "default";
		pinctrl-0 = <&cif_clk>, <&reset_gpio>, <&pwdn_gpio>; //<&power_gpio>
		//reset pin control by hardware,used this pin switch to mipi input
		//1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera
		reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
		pwdn-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
		rockchip,camera-module-index = <1>;
		rockchip,camera-module-facing = "front";
		rockchip,camera-module-name = "LMM248";//THDS11073
		rockchip,camera-module-lens-name = "YXC-M804A2"; //Largan-40122a1
		port {
			gc2145_out: endpoint {
				remote-endpoint = <&dphy2_in>;
				data-lanes = <1 2>;
			};
		};
	};

dts的配置就这些，只需要注意csi2_dphy对应的链路关系没有问题。接着结合原理图检查clock、和avdd-supply、dovdd-supply、dvdd-supply 三个电源以及使用到的gpio引脚是否配对正确。这样应该就没问题了，接着就是看驱动代码。