Documentation/arm/swp_emulation

最新推荐文章于 2022-10-01 18:12:28 发布

翻译最新推荐文章于 2022-10-01 18:12:28 发布 · 1.2k 阅读

本文深入探讨了ARMv6和v7架构下弃用的SWP/SWPB指令的软件仿真机制。详细解释了这些指令被推荐替换为更高效的LDREX和STREX指令的原因，以及在执行过程中遇到的内存访问故障如何通过LDREX/STREX或LDREXB/STREXB序列进行处理。此外，文章还介绍了如何通过/proc/cpu/swp_emulation查看与软件仿真相关的统计数据，以及在使用软件仿真时需要注意的潜在问题，特别是与全局监控和未缓存内存访问相关的风险。

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以下为正文

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Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
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弃用的软件仿真SWP指令（CONFIG_SWP_EMULATE）
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ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
moving to the load-locked/store-conditional instructions LDREX and STREX.

ARMv6架构不赞成使用SWP / SWPB指令,建议使用负载锁定/条件存储指令STREX和LDREX。

ARMv7 multiprocessing extensions introduce the ability to disable these
instructions, triggering an undefined instruction exception when executed.
Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
sequence. If a memory access fault (an abort) occurs, a segmentation fault is
signalled to the triggering process.

ARMv7的多重扩展引入了能够禁用这些指令，当执行时触发一个未定义的指令的异常。
残留的指令使用LDREX/ STREX或LDREXB/ STREXB的的仿真序列。如果存储器访问故障
（中止）发生时，分段故障信号会触发进程。

/proc/cpu/swp_emulation holds some statistics/information, including the PID of
the last process to trigger the emulation to be invocated. For example:
---
Emulated SWP: 12
Emulated SWPB: 0
Aborted SWP{B}: 1
Last process: 314
---

/proc/CPU/swp_emulation持有一些统计数字/表格信息，包括最后一道工序触发仿真所需要的PID。例如：
---
Emulated SWP: 12
Emulated SWPB: 0
Aborted SWP{B}: 1
Last process: 314
---

NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external
transaction monitoring block called a global monitor to maintain update
atomicity. If your system does not implement a global monitor, this option can
cause programs that perform SWP operations to uncached memory to deadlock, as
the STREX operation will always fail.

注意：当访问未缓存的共享区域，LDREX/ STREX依赖于外部事务监控块称为保持原子性更新的全球显示器。
如果您的系统没有实现一个全球性的显示器，这个选项可以导致程序执行SWP业务的未缓存的内存死锁，
STREX操作总是失败。