zzq275913866的博客

核间通信机制master/slave（主/从拓扑结构）/data flow（数据流拓扑结构）master/slave：主核（控制核）通过EDMA负责与外界DDR数据交换，通过中断与辅核通信，辅核只负责计算，之间无通信。data flow：基于片上互联的结构，每个核均有单独处理单元和存储媒介，第一个核与FPGA或外部DDR相连，核间通信顺序产生；每个核既是控制核又是计算核流程：identify a parallel task implementPartitioning >> commun

C6678板子CIC：chip interrupt controller(configure CPU interrupt) / 128 system events(internally-generated events and chip-level events) to be programmed to 12 CPU interruptmultiple events can be combined to a single event through chip level CIC.LSPC(local

两个dsp之间通过SRIO进行通信。device1 发送给device2，device2将数据乘以10并且返回device1。device01periphint();外设初始化Thread_Init(){Hwi_create(SRIODoorBellsr);Task_create(smain(传，接，验证));Task_create(DoorBelI_IntTsk) ;产生中断通知Semaphore_Params semparams sem = semaphore.create();}s

SYS/BIOSSYS/BIOS: Scalable real-time kernel require XDCtoolsXDCtools Modules: system services/memory management/diagnostics/synchronizationThreads: Hwi(timer)/Swi(clock)/Task/IdleSYS/BIOS任务线程有0-31个优先级（默认0-15，优先级0被空闲线程使用，任务最低优先级为1），但是在内存允许的情况下可以不限制的创建任

Rapid IO结构Peripheral data flow：Without interrupt to the CPUCommunicatiion Model: Direct I/O operaton / Message passing结构logical layer：protocols，packet formats，header，payloadtransport layer：route packetphysical layer（built-in PLL clock-recovery）：int