计算机组成原理vivado实验3

图5 程序计数器PC波形图

图6 regfile波形图

//pc设计代码
`timescale 1ns / 1ps
module pc(
    input wire clk,wire rst,
    output reg ce,reg[31:0] pc
    );
    always@(posedge clk)begin
        if(rst==1)
            ce<=0;
        else
            ce<=1;
    end
    always@(posedge clk)begin
        if(ce==0)
            pc<=32'h0;
        else
            pc<=pc+4;
    end
endmodule
//pc仿真代码
`timescale 1ns / 1ps
module pc_tb(

    );
    reg clk;
    reg rst;
    wire ce;
    wire[31:0] pc;
    pc pc1(clk,rst,ce,pc);
    initial begin
        clk=0;
        forever begin
            #5
            clk = ~clk;
        end
    end
    initial begin
        rst=1;
        #35
        rst = ~rst;           
        
    end
endmodule
//regfile设计代码
`timescale 1ns / 1ps

module regfile(
    input wire clk,rst,
    input wire re1,re2,we,
    input wire [4:0]raddr1,wire [4:0]raddr2,wire [4:0]waddr,
    input wire [31:0]wdata,
    output reg [31:0]rdata1,reg[31:0]rdata2

    );
    reg [31:0] regs[31:0];
    initial begin
        //regs[0]=32'h11223344;
        regs[1]=32'h33445566;
    end
    always@(posedge clk)begin
        if((rst==0)&&(we==1)&(waddr!=0))
            regs[waddr]<=wdata;
    end
    always@(*)begin
        if(rst==1)
            rdata1<=32'h0;
        else begin
            if((re1==1)&&(raddr1==0))
                rdata1<=0;
            else if((re1==1)&&(we==1)&&(raddr1==waddr))     
                rdata1<=wdata;           
            else if(re1==1)
                rdata1<=regs[raddr1];
            else
                rdata1<=0;
        end
    end
    always@(*)begin
        if(rst==1)
            rdata2<=32'h0;
        else begin
            if((re2==1)&&(raddr2==0))
                rdata2<=0;
            else if((re2==1)&&(we==1)&&(raddr2==waddr))     
                rdata2<=wdata;           
            else if(re2==1)
                rdata2<=regs[raddr2];
            else
                rdata2<=0;
        end
    end
endmodule
//regfile仿真代码
`timescale 1ns / 1ps
module regfile_tb(

    );
    reg clk,rst;
    reg re1,re2,we;
    reg [4:0]raddr1;reg [4:0]raddr2;reg [4:0]waddr;
    reg [31:0]wdata;
    wire [31:0]rdata1;wire[31:0]rdata2;
    regfile regfile1(
        clk,rst,
        re1,re2,we,
        raddr1,raddr2,waddr,
        wdata,
        rdata1,rdata2);
        
    initial begin
        clk = 0;
        forever begin
            #10 clk = ~clk;
        end
    end
    initial begin
        rst = 0;
        #60 rst = 1;
        #20 rst = 0;
    end
    initial begin
        re1 = 1;
        raddr1 = 5'h1;
        #5 re1 = 0;       
        we = 1;
        waddr = 5'h3;
        wdata = 32'h00000001;
        #10 we = 0;
        
        re2 = 1;
        raddr2 = 5'h3;
        #10
             
        #10 re1 = 1;
        raddr1 = 0;
        #10 re1 = 0;
        
        #5 we = 1;re1 = 1;
        waddr = 5'h1;
        raddr1 = 5'h1;
        wdata = 32'h00000002;
        #10 we = 0;re1 = 0;
        
        #10 we = 1;
        waddr = 5'h5;
        wdata = 32'h00000003;
        #10 we = 0;      
        re1 =1;
        raddr1 = 5'h5;
        #10 re1 = 0;       
    end
endmodule