FPGA|例化生成的PLL功能IP核

1、例化上一篇文章中调用的IP核，新建文件PLL_test.v

2、代码如图

`timescale 1ns / 1ps
module PLL_test(
						input clk,
						input rst_n,
						output clkout0,
						output clkout1,
						output clkout2,
						output clkout3,
						output clkout4
					);

wire locked;

PLL pll_inst(
					.inclk0(clk),
					
					.c0(clkout0),
					.c1(clkout1),
					.c2(clkout2),
					.c3(clkout3),
					.c4(clkout4),

					.areset(~rst_n),
					.locked(locked),
				);
endmodule

3、编译

4、设置引脚，选择assignments-》pin planner