<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[zhuangdk的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/zhuangdk</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; zhuangdk]]></copyright><item><title><![CDATA[SSN ( Streaming Scan Network ) 是什么？]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/128804337</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/128804337</guid><author>zhuangdk</author><pubDate>Mon, 30 Jan 2023 18:10:28 +0800</pubDate><description><![CDATA[大型片上系统(SoC)设计的复杂性不断增加，这对包括测试设计(DFT)在内的所有IC设计学科都提出了挑战。为了缓解这些挑战，层次DFT被用作一种分而治之的方法，其中所有DFT实现，包括模式生成和验证，都是在核心级别而不是芯片级别完成的。然而，层次DFT本身已经不够了。DFT工程师必须在测试实现工作和制造测试成本之间做出权衡。本文介绍了测试流扫描网络(SSN)的基本组成部分，SSN是一种封装测试交付技术，旨在解耦核心级和芯片级DFT需求。]]></description><category></category></item><item><title><![CDATA[SRAM 测试总结]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/128562028</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/128562028</guid><author>zhuangdk</author><pubDate>Thu, 05 Jan 2023 13:46:46 +0800</pubDate><description><![CDATA[SoC随着工艺进步设计复杂度增加，embeded sram也越来越多。在40nm SoC产品Sram一般在20Mbits左右，当工艺发展到28nm时Sram就增加到100Mbits。如果考虑AI产品，Sram估计更多。如何更好的测试Sram就成为量产测试的重中之重。

Sram的结构

一个6T sram cell的经典结构如图所示：



这些Sram cell集合成如下图的多个bank的memory block，每个bank有bank address使能；在一个bank内Row address选择]]></description><category></category></item><item><title><![CDATA[CheckPins]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/124038640</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/124038640</guid><author>zhuangdk</author><pubDate>Fri, 08 Apr 2022 12:49:00 +0800</pubDate><description><![CDATA[Extracted Timing Model Contains Internal Pins With the Name of the Master Clock

Description

Question:

In an extracted timing model (ETM), there is an internal pin with the name of the master clock. What is the reason for it?

Answer:

In an extracted ti]]></description><category></category></item><item><title><![CDATA[IC Open/Short/Leakage 测试]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122889880</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122889880</guid><author>zhuangdk</author><pubDate>Fri, 11 Feb 2022 22:38:49 +0800</pubDate><description><![CDATA[开短路测试(open_short_test)又叫continuity test 或contact test,它是一种非常快速发现芯片的各个引脚间的是否有短路，及在芯片封装时是否missing bond wires.通常都会被放测试程序的最前面.它还能发现测试时接触是否良好，探针卡或测试座是否有问题.

开短路测试的测试原理比较简单，分open_short_to_VDD 测试和open_short_to_VSS测试.一般来说芯片的每个引角都有泄放或说保护电路,是两个首尾相接的二...]]></description><category></category></item><item><title><![CDATA[Control Timings in VCS]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122202071</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122202071</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 20:30:39 +0800</pubDate><description><![CDATA[VCS/VCSMX can disable module path delays as well as timing checks at various levels 
of granularity viz. on the entire design, on a specific module or on a specific timing 
arc in a specific instance. 

1. Disabling delays and timing checks on the entire .]]></description><category></category></item><item><title><![CDATA[How Do Wrapper Chains and Wrapper Cells Work in Detail?]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122201878</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122201878</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 20:29:40 +0800</pubDate><description><![CDATA[Description

Question:

I am using the core wrapper feature of the DFTMAX tool. The user guide describes wrapper chain behavior from a high level, but it does not show detailed wrapper chain timing diagrams or logic schematics. In detail, how do wrapper ch]]></description><category></category></item><item><title><![CDATA[How do I make VCS ignore timing between synchronizer flops?]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122201858</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122201858</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 20:21:43 +0800</pubDate><description><![CDATA[Question:




How do I make VCS ignore SDF timing between synchronizer flip flops in my 
full timing gate simulation?


Answer:




VCS accepts  configuration file that can enable/disable certain features and 
options.One of these features is the ability t]]></description><category></category></item><item><title><![CDATA[How Are Clock Gating Checks Inferred?]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122201665</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122201665</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 20:18:23 +0800</pubDate><description><![CDATA[I have many clock gating checks in my design. Some of my clock gating checks are complex, where the gating signal is launched by a different clock than the clock being gated. What are the rules for how the setup and hold clock gating checks are inferred?

]]></description><category></category></item><item><title><![CDATA[How Does Clock Reconvergence Pessimism Removal (CRPR) Handle Dynamically Switched Related Clocks?]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122201597</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122201597</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 20:10:18 +0800</pubDate><description><![CDATA[I have a design in which a clock network switches between the original and divide-by-two version of a clock:







Figure 1: Clock Network

The clock switching circuitry is designed so that I can switch between them "on the fly" during the low portion of.]]></description><category></category></item><item><title><![CDATA[Why Is My CRPR Common Point Incorrect?]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122201439</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122201439</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 20:08:15 +0800</pubDate><description><![CDATA[I have a design with a path similar to the following:



Figure 1: Design Path

All buffers have min/max delays of 1ns/2ns, with the exception of U3 which has a slow delay of 1.9ns instead of 2ns (represented with a slightly smaller buffer symbol). When ..]]></description><category></category></item><item><title><![CDATA[CMOS Basics & Process Overview]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122201264</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122201264</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 19:54:53 +0800</pubDate><description><![CDATA[Why CMOS?

Output of all CMOS cells will be very close to rail-rail (may not be in case of Pass Transistor)
	With constant input to any cell, power dissipation is only due to leakage currents. Power dissipation increase if activity factor is more (Short ci]]></description><category></category></item><item><title><![CDATA[STA Part 2 by signoff-scribe]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122201073</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122201073</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 19:45:10 +0800</pubDate><description><![CDATA[Ways to fix setup violations:

Setup violation occurs because of high delay in the data path or due to negative skew.

Below are the ways to fix setup violation:

Gate sizing
	Buffering
	Cloning
	Logic restructuring
	Vt swapping
	Skewing


Gate Sizing:
Thi]]></description><category></category></item><item><title><![CDATA[Wire Modelling, Cross-talk & Double-switching]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122200993</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122200993</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 19:41:54 +0800</pubDate><description><![CDATA[Wire

Wire appears as a simple line in schematic diagrams, connecting two components. But they are equally important as transistors because they affect speed, power dissipation and reliability of the circuit.

Wire Model

Generally we think of wire to be i]]></description><category></category></item><item><title><![CDATA[STA – Part1]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122200932</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122200932</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 19:38:53 +0800</pubDate><description><![CDATA[What is STA ?

Static timing analysis is one of the techniques used to verify the timing of a digital design.
	
	STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pi]]></description><category></category></item><item><title><![CDATA[Clarification for SMS Wrapper synthesis and STA timing exceptions]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122200220</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122200220</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 19:02:56 +0800</pubDate><description><![CDATA[1.This section contains theexplanation of the timing exceptions forsn6xx000vpnnsmwrp000sa18SMS Wrapper.
Compared withSMS 5.x, where data exchange between fast and slow clock domains happens, in SMS 6x, due to the clock switching mechanism, communicati...]]></description><category></category></item><item><title><![CDATA[Multi chip package多芯片封装技术对比]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/122197727</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/122197727</guid><author>zhuangdk</author><pubDate>Tue, 28 Dec 2021 17:04:19 +0800</pubDate><description><![CDATA[1. 传统多芯片模块封装技术

Die 2 Die的通信是通过基板电路实现的，优点是可靠，缺点是集成的密度比较低。是一种非常原始的方式。



例子：amd Naples 的四个Chiplet之间的通信也是使用这种方式。





2. 使用硅中介层的封装技术 -2.5D封装

Silicon Interposer起承上启下的作用



缺点是：增加了厚度，增加了成本，所有Die出去的型号都要通过TSV技术过孔原本不必要，增加了成本。

目前工业界大部分的单封装的处理器基本都是这种封装技术。

例子：...]]></description><category></category></item><item><title><![CDATA[DFT compiler]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/121147865</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/121147865</guid><author>zhuangdk</author><pubDate>Thu, 04 Nov 2021 17:52:40 +0800</pubDate><description><![CDATA[scan

jtag

bist

ip
]]></description><category></category></item><item><title><![CDATA[IEEE std 1149.1 JTAG bscan 原理]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/121147801</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/121147801</guid><author>zhuangdk</author><pubDate>Thu, 04 Nov 2021 17:49:46 +0800</pubDate><description><![CDATA[jtag
]]></description><category></category></item><item><title><![CDATA[ATPG 基础]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/121147781</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/121147781</guid><author>zhuangdk</author><pubDate>Thu, 04 Nov 2021 17:48:37 +0800</pubDate><description><![CDATA[scan 测试
]]></description><category></category></item><item><title><![CDATA[STA - PVT、RC、OCV]]></title><link>https://blog.youkuaiyun.com/zhuangdk/article/details/118683334</link><guid>https://blog.youkuaiyun.com/zhuangdk/article/details/118683334</guid><author>zhuangdk</author><pubDate>Tue, 13 Jul 2021 21:23:08 +0800</pubDate><description><![CDATA[PVT

PVT是工艺、电压和温度的缩写。为了让我们的芯片在所有可能的条件下工作，比如在锡亚琴冰川-40°C和撒哈拉沙漠60°C，我们模拟了IC在制造后可能面临的不同过程、电压和温度的条件。这些条件称为corner。这三个参数都影响到cell的延时。我们将详细地讨论每个参数及其对延迟的影响。

Process:

工艺变化是指晶体管在制造过程中属性的偏差。

在裸片die制造过程中，die的中心和边界处的区域可能会有不同的工艺变化。这是因为将被制造的层不能在整...]]></description><category></category></item></channel></rss>