stm32 FSMC-外扩SRAM IS62WV51216

本文介绍了使用STM32的灵活静态内存控制器(FSMC)配置外部SRAM的过程。包括使能GPIO时钟、配置GPIO引脚模式、使能FSMC时钟、FSMC初始化及存储器块使能等步骤,并提供了具体的代码示例。

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引脚定义
12

FSMC配置步骤

1.使能对应引脚GPIO时钟
2.配置GPIO引脚模式
3.使能FSMC时钟
4.FSMC初始化
5.存储器块使能

举例
1


#define Bank1_SRAM3_ADDR    ((u32)(0x68000000))  //首地址0x60000000,每块0x40000000

void SRAM_gpio_init()
{
    GPIO_InitTypeDef gpiof = 
    {
        GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
            GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15, //FSMC_A0 - FSMC_A9
        GPIO_Speed_50MHz,
        GPIO_Mode_AF_PP
    };
    GPIO_InitTypeDef gpiog0_5 = 
    {
        GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5, //FSMC_A10 - FSMC_A15
        GPIO_Speed_50MHz,
        GPIO_Mode_AF_PP
    };
    GPIO_InitTypeDef gpiod = 
    {
        GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | //FSMC_A15 - FSMC_A18
        GPIO_Pin_14 | GPIO_Pin_15 | GPIO_Pin_0 | GPIO_Pin_1 | //FSMC_D0 - FSMC_D3
            GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10, //FSMC_D13 - FSMC_D15
        GPIO_Speed_50MHz,
        GPIO_Mode_AF_PP
    };
    GPIO_InitTypeDef gpioe = 
    {
        //FSMC_D4 - FSMC_D12
        GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15, 
        GPIO_Speed_50MHz,
        GPIO_Mode_AF_PP
    };

    GPIO_InitTypeDef gpioe0_1 = 
    {
        GPIO_Pin_0 | GPIO_Pin_1, //FSMC_NBL0-FSMC_NBL1
        GPIO_Speed_50MHz,
        GPIO_Mode_AF_PP
    };
    GPIO_InitTypeDef gpiod4_5 = 
    {
        GPIO_Pin_4 | GPIO_Pin_5, //FSMC_NOE - FSMC_NWE
        GPIO_Speed_50MHz,
        GPIO_Mode_AF_PP
    };
    GPIO_InitTypeDef gpiog10 = 
    {
        GPIO_Pin_10, //片选
        GPIO_Speed_50MHz,
        GPIO_Mode_AF_PP
    };

    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE, ENABLE);

    GPIO_Init(GPIOF, &gpiof);
    GPIO_Init(GPIOG, &gpiog0_5);
    GPIO_Init(GPIOD, &gpiod);
    GPIO_Init(GPIOE, &gpioe);
    GPIO_Init(GPIOE, &gpioe0_1);
    GPIO_Init(GPIOD, &gpiod4_5);
    GPIO_Init(GPIOG, &gpiog10);
}

void FSMC_sram_init()
{
    FSMC_NORSRAMInitTypeDef fsmc = {0};
    FSMC_NORSRAMTimingInitTypeDef FSMC_ReadWriteTimingStruct = {0};

    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);

    FSMC_ReadWriteTimingStruct.FSMC_AddressSetupTime = 0x00;
    FSMC_ReadWriteTimingStruct.FSMC_AddressHoldTime = 0x00;
    FSMC_ReadWriteTimingStruct.FSMC_DataSetupTime = 0x08;
    FSMC_ReadWriteTimingStruct.FSMC_BusTurnAroundDuration = 0x00;
    FSMC_ReadWriteTimingStruct.FSMC_CLKDivision = 0x00;
    FSMC_ReadWriteTimingStruct.FSMC_DataLatency = 0x00;
    FSMC_ReadWriteTimingStruct.FSMC_AccessMode = FSMC_AccessMode_A;

    fsmc.FSMC_Bank = FSMC_Bank1_NORSRAM3;
    fsmc.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
    fsmc.FSMC_MemoryType = FSMC_MemoryType_SRAM;
    fsmc.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
    fsmc.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
    fsmc.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
    fsmc.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
    fsmc.FSMC_WrapMode = FSMC_WrapMode_Disable;
    fsmc.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
    fsmc.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
    fsmc.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
    fsmc.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable; //扩展模式使能
    fsmc.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
    fsmc.FSMC_ReadWriteTimingStruct = &FSMC_ReadWriteTimingStruct;
    fsmc.FSMC_WriteTimingStruct = &FSMC_ReadWriteTimingStruct;
    FSMC_NORSRAMInit(&fsmc);

    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
}

void SRAM_read(u8 *buf, u32 addr, u32 num)
{
    u32 i = 0;

    for(i = 0; i < num; i++)
    {
        buf[i] = *(u8*)(Bank1_SRAM3_ADDR + addr + i);
    }
}

void SRAM_write(u8 *buf, u32 addr, u32 num)
{
    u32 i = 0;
    u8 *p = (u8*)(Bank1_SRAM3_ADDR + addr);

    for(i = 0; i < num; i++)
    {
        *(p + i) = buf[i];
    }
}
### STM32 FSMC SRAM 配置 #### 初始化配置 为了使STM32能够访问SRAM,需要通过灵活静态存储器控制器(FSMC)来完成硬件接口的搭建。FSMC支持多种类型的内存设备连接,包括SRAM、PSRAM以及NOR Flash等。 针对SRAM的操作,主要涉及以下几个方面: - **地址/数据总线复用模式**:根据具体需求决定是否启用地址和数据总线复用功能[^2]。 - **读写等待周期设定**:考虑到不同型号SRAM的工作频率差异较大,适当调整读取或写入操作期间所需的等待时间有助于提高系统的稳定性与性能。 - **片选信号管理**:合理规划多个部器件共存情况下的芯片选择机制,确保每次仅激活目标设备而不会干扰到其它部件正常工作。 以下是基于CubeMX工具生成初始化代码的一个简化版本,适用于大多数场景下对SRAM进行读写的场合。 ```c // 定义使用的库头文件 #include "stm32f1xx_hal.h" /* FSMC_NORSRAM Init Structure definition */ static FSMC_NORSRAM_TimingTypeDef Timing = { .AddressSetupTime = 15, .AddressHoldTime = 0, .DataSetupTime = 16, .BusTurnAroundDuration = 0, .CLKDivision = 16, /* Only used when asynchronous mode is enabled and CLKDIV != 0 */ .DataLatency = 17, .AccessMode = FSMC_ACCESS_MODE_A }; void MX_FSMC_Init(void){ __HAL_RCC_FSMC_CLK_ENABLE(); // 启用FSMC时钟 /** Perform the SRAM1 memory initialization sequence */ fsmc_norsram_initialize(&hsram1); } /** * @brief Initializes the NOR/SRAM Bank according to specified parameters. * This function configures all necessary registers for communication with external memories connected via FSMC interface. * * @param hnor Instance of NORSRAM_HandleTypeDef structure that contains configuration information about specific bank being initialized. */ static void fsmc_norsram_initialize(NORSRAM_HandleTypeDef* hnor) { FSMC_NORSRAM_InitTypeDef NSInit; /* Configure common properties shared among banks within same controller instance */ NSInit.NSBank = FSMC_NORSRAM_BANK1; /*!< Selects which physical bank will be configured by this call */ NSInit.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;/* Disables multiplexing between address lines A[23:0] & data bus DQ[15:0]. Separate buses are preferred here.*/ NSInit.MemoryType = FSMC_MEMORY_TYPE_SRAM; /*!< Specifies type of attached device as Static RAM*/ NSInit.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;//< Sets width of both internal processor's data path & external component’s I/O port size equal to 16 bits wide. NSInit.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;/* Continuous read operations aren't supported on simple static rams so disable burst transfers.*/ NSInit.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW ;/* Active low wait signal polarity matches typical sram specifications.*/ NSInit.WrapBurstMode = FSMC_WRAP_BURST_MODE_DISABLE; /* No wrapping required since we're dealing only with linear addresses space access patterns.*/ NSInit.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; /* Enable write capability allowing us full control over contents stored inside ram chip.*/ NSInit.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; /* Wait state inserted before actual transfer occurs ensuring reliable operation even at higher frequencies.*/ NSInit.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;/* Synchronous mode provides better timing accuracy compared against async alternative especially important during debug sessions where trace probes might introduce additional delays into system clock tree distribution network affecting overall performance characteristics observed from outside perspective looking inwards towards target board under test conditions.*/ NSInit.ModeExtender = FSMC_EXTENDED_MODE_DISABLE; if(HAL_OK != HAL_SRAM_Init(hnor,&NSInit,&Timing)) { Error_Handler(); } } ``` 这段程序展示了如何利用STM32的标准设驱动函数库(HAL Library)来进行必要的寄存器级编程以实现对特定品牌型号SRAM芯片的支持。实际应用中可能还需要考虑更多细节因素如电源电压范围匹配度校验等问题才能保证最佳效果。
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